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EP2AGX260EF29C5N Datasheet(PDF) 8 Page - Altera Corporation |
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EP2AGX260EF29C5N Datasheet(HTML) 8 Page - Altera Corporation |
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8 / 78 page  1–8 Chapter 1: Device Datasheet for Arria II Devices Electrical Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum July 2012 Altera Corporation I/O Pin Leakage Current Table 1–7 lists the Arria II GX I/O pin leakage current specifications. Table 1–8 lists the Arria II GZ I/O pin leakage current specifications. Bus Hold Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode. Table 1–9 lists bus hold specifications for Arria II GX devices. Table 1–7. I/O Pin Leakage Current for Arria II GX Devices Symbol Description Conditions Min Typ Max Unit II Input pin VI = 0 V to VCCIOMAX –10 — 10 µA IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX –10 — 10 µA Table 1–8. I/O Pin Leakage Current for Arria II GZ Devices Symbol Description Conditions Min Typ Max Unit II Input pin VI = 0 V to VCCIOMAX –20 — 20 µA IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX –20 — 20 µA Table 1–9. Bus Hold Parameters for Arria II GX Devices (Note 1) Parameter Symbol Cond. VCCIO (V) Unit 1.2 1.5 1.8 2.5 3.0 3.3 Min Max Min Max Min Max Min Max Min Max Min Max Bus-hold low, sustaining current ISUSL VIN > VIL (max.) 8 — 12 — 30—50 — 70 — 70 — µA Bus-hold high, sustaining current ISUSH VIN < VIL (min.) –8 — –12 — –30 — –50 — –70 — –70 — µA Bus-hold low, overdrive current IODL 0V <VIN < VCCIO — 125 — 175 — 200 — 300 — 500 — 500 µA Bus-hold high, overdrive current IODH 0V <VIN < VCCIO — –125 — –175 — –200 — –300 — –500 — –500 µA Bus-hold trip point VTRIP — 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V Note to Table 1–9: (1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard. |
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