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SMJ320F240 Datasheet(PDF) 6 Page - Texas Instruments |
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SMJ320F240 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 104 page  SMJ320F240 DSP CONTROLLER SGUS029C -- APRIL 1999 -- REVISED SEPTEMBER 2004 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 Terminal Functions (Continued) TERMINAL TYPE† DESCRIPTION NAME NO. TYPE† DESCRIPTION BIT I/O AND SHARED FUNCTIONS PINS (CONTINUED) T1PWM/T1CMP/ IOPB3 105 I/O/Z Bidirectional digital I/O. Timer 1 compare output. T1PWM/T1CMP/IOPB3 goes to the high-impedance state when unmasked PDPINT goes active low. This pin is configured as a digital input by all device resets. T2PWM/T2CMP/ IOPB4 106 I/O/Z Bidirectional digital I/O. Timer 2 compare output. T2PWM/T2CMP/IOPB4 goes to the high- impedance state when unmasked PDPINT goes active low. This pin is configured as a digital input by all device resets. T3PWM/T3CMP/ IOPB5 107 I/O/Z Bidirectional digital I/O. Timer 3 compare output. T3PWM/T3CMP/IOPB5 goes to the high-impedance state when unmasked PDPINT goes active low. This pin is configured as a digital input by all device resets. TMRDIR/IOPB6 108 I/O Bidirectional digital I/O. Direction signal for the timers. Up-counting direction if TMRDIR/IOPB6 is low, down-counting direction if this pin is high. This pin is configured as a digital input by all device resets. TMRCLK/IOPB7 109 I/O Bidirectional digital I/O. External clock input for general-purpose timers. This pin is configured as a digital input by all device resets. ADCSOC/IOPC0 63 I/O Bidirectional digital I/O. External start of conversion input for ADC. This pin is configured as a digital input by all device resets. CAP1/QEP1/IOPC4 67 I/O Bidirectional digital I/O. Capture 1 or QEP 1 input. This pin is configured as a digital input by all device resets. CAP2/QEP2/IOPC5 68 I/O Bidirectional digital I/O. Capture 2 or QEP 2 input. This pin is configured as a digital input by all device resets. CAP3/IOPC6 69 I/O Bidirectional digital I/O. Capture 3 input. This pin is configured as a digital input by all device resets. CAP4/IOPC7 70 I/O Bidirectional digital I/O. Capture 4 input. This pin is configured as a digital input by all device resets. XF/IOPC2 65 I/O Bidirectional digital I/O. External flag output (latched software-programmable signal). XF is used for signaling other processors in multiprocessing configurations or as a general-purpose output pin. This pin is configured as an external flag output by all device resets. BIO/IOPC3 66 I/O Bidirectional digital I/O. Branch control input. BIO is polled by the BIOZ instruction. If BIO is low, the CPU executes a branch. If BIO is not used, it should be pulled high. This pin is configured as a branch-control input by all device resets. CLKOUT/IOPC1 64 I/O Bidirectional digital I/O. Clock output. Clock output is selected by the CLKSRC bits in the SYSCR register. This pin is configured as a DSP clock output by a power-on reset. SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS SCITXD/IO 44 I/O SCI asynchronous serial port transmit data, or general-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. SCIRXD/IO 43 I/O SCI asynchronous serial port receive data, or general-purpose bidirectional I/O. This pin is configured as a digital input by all device resets. † I = input, O = output, Z = high impedance |
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