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BQ2018 Datasheet(PDF) 8 Page - Texas Instruments |
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BQ2018 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 25 page  8 low-power mode until HDQ goes high, indicating an ex- ternal system is ready to access the bq2018. If HDQ transitions high prior to completion of the V OS calculation or if |VSR|>VWOE, then the calibration cycle is reset. The bq2018 then postpones the calibration cycle until the conditions are met. The calibration bit does not reset to zero until a valid calibration cycle is completed. The re- quirement for HDQ to remain low for the calibration cy- cle can be disabled by setting the OVRDQ bit to 1. In this case, calibration continues as long as |VSR|<VWOE. The OVRDQ bit is reset to zero at the end of a valid calibra- tion cycle. Communicating with the bq2018 The bq2018 includes a simple single-pin (referenced to VSS) serial data interface. A host processor uses the in- terface to access various bq2018 registers. Battery activ- ity may be easily monitored by adding a single contact to the battery pack. Note: The HDQ pin requires an ex- ternal pull-up or pull-down resistor. The interface uses a command-based protocol, where the host processor sends a command byte to the bq2018. The command directs the bq2018 either to store the next eight bits of data received to a register specified by the command byte or to output the eight bits of data from a register specified by the command byte. The communication protocol is asynchronous return-to- one. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 5K bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. Data input from the bq2018 may be sampled using the pulse-width capture timers available on some microcontrollers. A UART may also be used to communicate through the HDQ pin. If a communication time-out occurs, e.g., the host waits longer than tCYCB for the bq2018 to respond or if this is the first access command, then a BREAK should be sent by the host. The host may then resend the command. The bq2018 detects a BREAK when the HDQ pin is driven to a logic-low state for a time, tB or greater. The HDQ pin then returns to its normal ready-high logic state for a time, tBR. The bq2018 is then ready to receive a com- mand from the host processor. The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmis- sion by either the host or the bq2018 taking the HDQ pin to a logic-low state for a period, tSTRH,B. The next section is the actual data transmission, where the data should be valid by a period, tDSU,B, after the negative edge used to start communication. The data should be held for a peri- od, tDV/tDH, to allow the host or bq2018 to sample the data bit. The final section is used to stop the transmission by re- turning the HDQ pin to a logic-high state by at least a period, tSSU,B, after the negative edge used to start com- munication. The final logic-high state should be held un- til a period, tCYCH,B, to allow time to ensure that the bit transmission ceased properly. The serial communication timing specification and illustration sections give the timings for data and break communication. Communication with the bq2018 always occurs with the least-significant bit being transmitted first. Figure 4 shows an example of a communication sequence to read the bq2018 OFR register. bq2018 Registers The bq2018 command and status registers are listed in Table 5 and described below. Command (CMDR) The write-only command register is accessed when the bq2018 has received eight contiguous valid command bits. The command register contains two fields: n W/R n Command address The W/R bit of the command register is used to select whether the received command is for a read or a write function. The W/R values are CMDR Bits 76 5 4 3 2 1 0 W/R - -- - - - - Where W/R is 0 The bq2018 outputs the requested register contents specified by the address portion of the CMDR 1 The following eight bits should be written to the register specified by the address por- tion of the CMDR The lower seven-bit field of CMDR contains the address portion of the register to be accessed. CMDR Bits 76 5 4 3 2 1 0 - AD6 AD5 AD4 AD3 AD2 AD1 AD0 Discharge Count Registers (DCRH/DCRL) The DCRH high-byte register (address = 7fh) and the DCRL low-byte register (address = 7eh) contain the count bq2018 |
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