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BQ20Z75DBT-V180 Datasheet(PDF) 3 Page - Texas Instruments |
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BQ20Z75DBT-V180 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 23 page bq20z75-V180 www.ti.com SLUSA22 – DECEMBER 2009 TERMINAL FUNCTIONS TERMINAL I/O(1) DESCRIPTION NO. NAME 1 DSG O High side N-channel discharge FET gate drive Battery pack input voltage sense input. It also serves as device wake up when device is in shutdown 2 PACK IA, P mode. Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to 3 VCC P ensure device supply either from battery stack or battery pack input 4 ZVCHG O P-channel pre-charge FET gate drive High voltage general purpose open drain output. Can be configured to be used in pre-charge 5 GPOD OD condition Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET 6 PMS I connected at CHG pin. Connect to VSS to disable 0V pre-charge using charge FET connected at CHG pin. 7 VSS P Negative device power supply input. Connect all VSS pins together for operation of device 8 REG33 P 3.3V regulator output. Connect at least a 2.2 μF capacitor to REG33 and VSS 9 TOUT P Termistor bias supply output 10 VCELL+ - Internal cell voltage multiplexer and amplifier output. Connect a 0.1 μF capacitor to VCELL+ and VSS Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will 11 ALERT I/OD be triggered. 12 PRES I/OD System / Host present input. Pull up to TOUT 13 TS1 IA Temperature sensor 1 input 14 TS2 IA Temperature sensor 2 input 15 PFIN I/OD Fuse blow detection input 16 SAFE I/OD blow fuse signal output 17 SMBD I/OD SMBus data line 18 SMBC I/OD SMBus clock line 19 NC - Not Connected 20 VSS P Negative device power supply input. Connect all VSS pins together for operation of device. 21 VSS P Negative device power supply input. Connect all VSS pins together for operation of device. 22 GSRP IA Coulomb counter differential input. Connect to one side of the sense resistor 23 GSRN IA Coulomb counter differential input. Connect to one side of the sense resistor 24 MRST I Reset input for internal CPU core. connect to RESET for correct operation of device. 25 VSS P Negative device power supply input. Connect all VSS pins together for operation of device. 26 REG25 P 2.5V regulator output. Connect at least a 1 μF capacitor to REG25 and VSS RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of 27 RBI P short-circuit condition 28 VSS P Negative device power supply input. Connect all VSS pins together for operation of device 29 RESET O Reset output. Connect to MSRT. 30 ASRN IA Short-circuit and overload detection differential input 31 ASRP IA Short-circuit and overload detection differential input Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell 32 VC5 IA,P stack. Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the 33 VC4 IA,P negative voltage of the second lowest cell in cell stack. Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in 34 VC3 IA,P cell stack and the negative voltage of the second highest cell in 4 cell applications. Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell 35 VC2 IA,P and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2 cell stack applications Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell 36 VC1 IA,P stack in 4 cell applications. Connect to VC2 in 3 or 2 cell stack applications (1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): bq20z75-V180 |
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