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SN75DP122RTQT Datasheet(PDF) 7 Page - Texas Instruments |
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SN75DP122RTQT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 37 page  DEVICE POWER ELECTRICAL CHARACTERISTICS HOT PLUG AND CABLE ADAPTER DETECT ELECTRICAL CHARACTERISTICS SWITCHING CHARACTERISTICS SN75DP122 www.ti.com......................................................................................................................................... SLLS892A – FEBRUARY 2008 – REVISED NOVEMBER 2008 The SN75DP122 is designed to operate off of two supply voltages. The DisplayPort port and the digital logic run off of the 5V supply voltage. The TMDS level translator is powered off of the 3.3V supply. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDD LP = 5 V, VDD *1 = V DD, Priority = 0 V 60 65 ML: VID = 600 mV, 2.7 Gbps PRBS Supply current mA AUX: VID = 500 mV, 1 Mbps PRBS ICC 0.1 0.25 DP/TMDS_HPD_SINK and CAD_SINK = 5 V IDD(2) LP = 5 V, VDD *1 = V DD, Priority = 1 V 2 4 ML: VID = 500 mV, 2.5 Gbps PRBS Supply current mA AUX: VI = 2 V, 100 kHz ICC(2) 80 110 DP/TMDS_HPD_SINK and CAD_SINK = 5 V IDD *1 Supply current VDD *1 = 5.25 V 0.1 4 mA ISD Shutdown current LP = 0 V 1 16 µA The SN75DP122 is designed to support the switching of the Hot Plug Detect and Cable adapter Detect signals. The SN75DP122 has a built in level shifter for the HPD and CAD outputs. The output voltage level of the HPD and CAD pins is defined by the voltage level of the VDD *1 pin. When the DisplayPort port is selected, the state of CAD_SINK is propagated to the CAD output pin. If the TMDS port is selected, the CAD output pin stays HIGH as long as that port is selected. Explanation of HPD and the internal logic of the SN75DP122 is located in the application section at the end of the data sheet. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH5 High-level output voltage IOH = –100 µA, VDD *1 = 5 V 4.5 5 V VOH3.3 High-level output voltage IOH = –100 µA, VDD *1 = 3.3 V 3 3.3 V VOH2.5 High-level output voltage IOH = –100 µA, VDD *1 = 2.5 V 2.25 2.5 V VOH1.8 High-level output voltage IOH = –100 µA, VDD *1 = 1.8 V 1.62 1.8 V VOL Low-level output voltage IOH = 100 µA, 0 0.4 V IH High-level input current VIH = 2.0 V, VDD = 5.25 V –10 10 µA IL Low-level input current VIL = 0.8 V, VDD = 5.25 V –10 10 µA over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPD(CAD) Propagation delay VDD *1 = 5 V 5 30 ns tPD(HPD) Propagation delay VDD *1 = 5 V 30 110 ns tT1(HPD) HPD logic switch pause time VDD *1 = 5 V 2 4.7 ms tT2(HPD) HPD logic switch time VDD *1 = 5 V 170 400 ms tM(HPD) Minimum output pulse duration VDD *1 = 5 V 100 ns tZ(HPD) Low power to high-level propagation delay VDD *1 = 5 V 30 50 110 ns Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): SN75DP122 |
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