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TPS54610PWP Datasheet(PDF) 5 Page - Texas Instruments |
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TPS54610PWP Datasheet(HTML) 5 Page - Texas Instruments |
5 / 24 page www.ti.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH PH PH PH PH RT SYNC SS/ENA VBIAS VIN VIN VIN VIN VIN PGND PGND PGND PGND PGND PWP PACKAGE (TOP VIEW) THERMAL PAD TPS54610 SLVS398F – JUNE 2001 – REVISED APRIL 2007 Terminal Functions TERMINAL DESCRIPTION NAME NO. Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and AGND 1 SYNC pin. Connect PowerPAD to AGND. Bootstrap output. 0.022- µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the BOOT 5 high-side FET driver. COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas PGND 15-19 to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to AGND is recommended. PH 6-14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. Power good open drain output. High when VSENSE ≥ 90% V ref, otherwise PWRGD is low. Note that output is low when PWRGD 4 SS/ENA is low or the internal shutdown signal is active. Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the RT 28 SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency. Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and SS/ENA 26 capacitor input to externally set the start-up time. Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select SYNC 27 between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin. Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a VBIAS 25 high quality, low-ESR 0.1- µF to 1.0-µF ceramic capacitor. Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to VIN 20-24 device package with a high quality, low-ESR 10- µF ceramic capacitor. VSENSE 2 Error amplifier inverting input. Connect to output voltage through compensation network/output divider. 5 Submit Documentation Feedback |
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