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TMS320DM6467CZUT Datasheet(PDF) 5 Page - Texas Instruments |
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TMS320DM6467CZUT Datasheet(HTML) 5 Page - Texas Instruments |
5 / 355 page Switched Central Resource (SCR) JTAG Interface System Control PLLs/Clock Generator Power/Sleep Controller Pin Multiplexing ARM Subsystem ARM926EJ-S CPU 16KB I-Cache 32KB RAM 8KB D-Cache 8KB ROM DSP Subsystem C64x+ DSP CPU TM 32KB L1 Pgm 128KB L2 RAM 32KB L1 Data High-Definition Video-Imaging Coprocessor (HDVICP0) Input Clock(s) High-Definition Video-Imaging Coprocessor (HDVICP1) Peripherals EDMA I2C SPI UART Serial Interfaces DDR2 Mem Ctlr (16b/32b) Async EMIF/ NAND/ SmartMedia ATA Program/Data Storage Watchdog Timer PWM System General- Purpose Timer USB 2.0 PHY VLYNQ EMAC With MDIO Connectivity HPI McASP Video Port I/F PCI (33 MHz) TSIF CRGEN VDCE TMS320DM6467 www.ti.com SPRS403H – DECEMBER 2007 – REVISED JUNE 2012 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the device. Figure 1-1. TMS320DM6467 Functional Block Diagram Copyright © 2007–2012, Texas Instruments Incorporated Digital Media System-on-Chip (DMSoC) 5 Submit Documentation Feedback Product Folder Link(s): TMS320DM6467 |
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