HMC1001/1002/1021/1022

10

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Figure 4 – Higher Voltage Set/Reset Circuit for HMC1001 & HMC1002

The three strap resistances are chosen at 1.8 ohms, or the worst-case high resistance points. Since they require a

minimum of 3 amperes peak, the series combination requires at least 16.2 volts, so a circuit Vdd of about 18 volts would

about the right level to drive the strap load and allocate for losses in the C1 capacitor ESR and the MOSFET switches X1

and X2. C1’s value is also chosen at 0.22 micro-farad so the circuit time constant is at least around 1 micro-second.

Supply reservoir capacitor C2 is chosen to many times the value of C1 and is also picked for small size, working voltage,

and low ESR relative to the strap load resistance. C2 typically will be in the 1 to 10 micro-farad range and best to error on

the high capacitance side since C2 now supplies additional X1 gate drive circuitry. Resistor R5 is then chosen after C2 to

set the recharge time constant and to limit peak supply current. These capacitors should be chosen to have a low ESR

characteristic of around 0.2 ohms per capacitor.

Working backwards from the strap load resistance, MOSFETs X1 and X2 are chosen as IRF7105 due to the total

packaged size (both X1 and X2 in one SOIC-8), and meeting the requirements for operating voltages, peak currents, and

low on resistances. X2 is directly driven from digital logic denoted as “Vset”, and “Vreset” drives the level shifting sub-

circuit to X1. Note that Vreset turns off X2 first prior to X1 being driven on by Vset, and also X1 is turned off before X2 is

turned on. While one logic line could control the operation of Vset and Vreset, the additional inverter stages and pulse

delay components may be too space and cost consuming compared to two logic ports in a microcontroller. See Figure 4

in Application Note 201 for the discrete Vset and Vreset pulse forming circuit.

Transistors Q1 and Q2 in Figure 4 are chosen to be generic BJTs to force MOSFET X1’s gate charge quickly into on and

off states. Resistors R1 and R2 are selected as nominal 1000 ohm values that can pump or dump X1’s gate charge by

supplying Q1 and Q2 with enough base drive currents to flip their on and off states. Transistor Q3 is also chosen as a

generic, but reasonably fast switch transistor to perform the level shift function with resistors R1 and R2. Components R3,

C3 and D1 are chosen to properly drive Q3 from a logic level source, with C3 and D1 denoted as a “speed-up” network to

quickly switch Q3 within a few nanoseconds of logic transitions.

5

1

2

X1

IRF7105P

8

X2

IRF7105N

3

Q1

2N2222

Q2

2N2907

R1

1000

4

R2

1000

6

Q3

2N2222

7

R3

1000

10

Vdd

Vset

Vreset

12

Rsr3

1.8

9

C1

0.22U

C2

10U

R5

220

C3

1N

D1

1N4148

11

Rsr1

1.8

Rsr2

1.8