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NM24C02FVMT8 Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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NM24C02FVMT8 Datasheet(HTML) 11 Page - Fairchild Semiconductor |
11 / 14 page 11 www.fairchildsemi.com NM24C02/03 Rev. G Write Operations BYTE WRITE For a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. Upon receipt of the byte address the NM24C02/03 responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the NM24C02/ 03 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the NM24C02/03 inputs are disabled, and the device will not respond to any requests from the master for the duration of t WR. Refer to Figure 4 for the address, acknowledge and data transfer sequence. PAGE WRITE To minimize write cycle time, NM24C02/03 offer Page Write feature, by which, up to a maximum of 16 contiguous bytes locations can be programmed all at once (instead of 16 individual byte writes). To facilitate this feature, the memory array is orga- nized in terms of “Pages.” A Page consists of 16 contiguous byte locations starting at every 16-Byte address boundary (for ex- ample, starting at array address 0x00, 0x10, 0x20 etc.). Page Write operation limits access to byte locations within a page. In other words a single Page Write operation will not cross over to locations on another page but will “roll over” to the beginning of the page whenever end of Page is reached and additional locations are a continued to be accessed. A Page Write operation can be initiated to begin at any location within a page (starting address of the Page Write operation need not be the starting address of a Page). S T O P Bus Activity: Master SDA Line Bus Activity: EEPROM DATA n + 15 DATA n + 1 DATA n WORD ADDRESS (n) A C K S T A R T SLAVE ADDRESS A C K A C K A C K A C K S T O P A C K DATA A C K A C K S T A R T WORD ADDRESS SLAVE ADDRESS Bus Activity: Master SDA Line Bus Activity: EEPROM DS500069-13 DS500069-14 Page Write is initiated in the same manner as the Byte Write operation; but instead of terminating the cycle after transmitting the first data byte, the master can further transmit up to 15 more bytes. After the receipt of each byte, NM24C02/03 will respond with an acknowledge pulse, increment the internal address counter to the next address and is ready to accept the next data. If the master should transmit more than sixteen bytes prior to generat- ing the STOP condition, the address counter will “roll over” and previously written data will be overwritten. As with the Byte Write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 5 for the address, acknowledge and data transfer sequence. Acknowledge Polling Once the stop condition is issued to indicate the end of the host’s write operation the NM24C02/03 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the NM24C02/03 is still busy with the write operation no ACK will be returned. If the NM24C02/03 has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation. Write Protection (NM24C03 Only) Programming of the upper half (upper 1Kbit) of the memory will not take place if the WP pin of the NM24C03 is connected to VCC. The NM24C03 will respond to slave and byte addresses; but if the memory accessed is write protected by the WP pin, the NM24C03 will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. Byte Write (Figure 4) Page Write (Figure 5) |
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