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VCCIB5 Datasheet(PDF) 2 Page - Microsemi Corporation |
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VCCIB5 Datasheet(HTML) 2 Page - Microsemi Corporation |
2 / 212 page Military ProASIC3/EL Low Power Flash FPGAs II Revision 3 I/Os Per Package 1 Military ProASIC3/EL Device Status ProASIC3/EL Low Power Devices A3P250 A3PE600L A3P1000 A3PE3000L ARM Cortex-M1 Devices M1A3P1000 M1A3PE3000L Package Single- Ended I/O2 Differential I/O Pairs Single- Ended I/O2 Differential I/O Pairs Single- Ended I/O2 Differential I/O Pairs Single- Ended I/O2 Differential I/O Pairs VQ100 68 13 – – – – – – PQ208 – – – – 154 35 – – FG144 – – – – 97 25 – – FG484 – – 270 135 300 74 341 168 FG896 – – – – – – 620 300 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure you are complying with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. "G" indicates RoHS-compliant packages. Refer to "Military ProASIC3/EL Ordering Information" on page III for the location of the "G" in the part number. 4. For A3PE3000L devices, the usage of certain I/O standards is limited as follows: – SSTL3(I) and (II): up to 40 I/Os per north or south bank – LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank – SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user I/Os available is reduced by one. Military ProASIC3/EL Devices Status M1 Military ProASIC3/EL Devices Status A3P250 Production A3PE600L Production A3P1000 Production M1A3P1000 Production A3PE3000L Production M1A3PE3000L Production |
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