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ADSP-2181KS-115 Datasheet(PDF) 6 Page - Analog Devices |
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ADSP-2181KS-115 Datasheet(HTML) 6 Page - Analog Devices |
6 / 32 page REV. D ADSP-2181 –6– When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to in- coming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2181 will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64 or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). SYSTEM INTERFACE Figure 2 shows a typical basic system configuration with the ADSP-2181, two serial devices, a byte-wide EPROM, and op- tional external program and data overlay memories. Program- mable wait state generation allows the processor to connect easily to slow peripheral devices. The ADSP-2181 also provides four external interrupts and two serial ports or six external inter- rupts and one serial port. 1/2x CLOCK OR CRYSTAL SERIAL DEVICE SERIAL DEVICE 16 A0-A21 DATA CS BYTE MEMORY I/O SPACE (PERIPHERALS) CS DATA ADDR DATA ADDR 2048 LOCATIONS OVERLAY MEMORY TWO 8K PM SEGMENTS TWO 8K DM SEGMENTS D23-0 A13-0 D23-8 A10-0 D15-8 D23-16 A13-0 14 24 SPORT1 SCLK0 RFS0 TFS0 DT0 DR0 SPORT0 IAD15-0 IDMA PORT FL0-2 PF0-7 CLKIN XTAL ADDR13-0 DATA23-0 BMS IOMS ADSP-2181 RD WR IRQ2 IRQE IRQL0 IRQL1 PMS DMS CMS BR BG BGH PWD PWDACK IRD IWR IS IAL IACK SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI SYSTEM INTERFACE OR CONTROLLER Figure 2. ADSP-2181 Basic System Configuration Clock Signals The ADSP-2181 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal opera- tion. The only exception is while the processor is in the power- down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’s Manual, Third Edition, for detailed information on this power-down feature. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is con- nected to the processor’s CLKIN input. When an external clock is used, the XTAL input must be left unconnected. The ADSP-2181 uses an input clock with a frequency equal to half the instruction rate; a 20.00 MHz input clock yields a 25 ns processor cycle (which is equivalent to 40 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. Because the ADSP-2181 includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register. CLKIN CLKOUT XTAL DSP Figure 3. External Crystal Connections Reset The RESET signal initiates a master reset of the ADSP-2181. The RESET signal must be asserted during the power-up se- quence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is ap- plied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the mini- mum pulse width specification, tRSP. The RESET input contains some hysteresis; however, if you use an RC circuit to generate your RESET signal, the use of an external Schmidt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting (MMAP = 0), the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. |
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