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AD9739BBCZ Datasheet(PDF) 5 Page - Analog Devices

Part # AD9739BBCZ
Description  14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

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Data Sheet
AD9739
Rev. B | Page 5 of 48
LVDS DIGITAL SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-
1996 reduced range link, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1
Input Common-Mode Voltage Range, VCOM
825
1575
mV
Logic High Differential Input Threshold, VIH_DTH
175
400
mV
Logic Low Differential Input Threshold, VIL_DTH
−175
−400
mV
Receiver Differential Input Impedance, RIN
80
120
Ω
Input Capacitance
1.2
pF
LVDS Input Rate
1250
MSPS
LVDS Minimum Data Valid Period, tVALID (See Figure 41)
344
ps
LVDS CLOCK INPUT (DCI and SYNC_IN)2
Input Common-Mode Voltage Range, VCOM
825
1575
mV
Logic High Differential Input Threshold, VIH_DTH
175
400
mV
Logic Low Differential Input Threshold, VIL_DTH
−175
−400
mV
Receiver Differential Input Impedance, RIN
80
120
Ω
Input Capacitance
1.2
pF
Maximum Clock Rate
625
MHz
LVDS CLOCK OUTPUT (DCO and SYNC_OUT)3
Output Voltage High (x_P or x_N)
1375
mV
Output Voltage Low (x_P or x_N)
1025
mV
Output Differential Voltage, |VOD|
150
200
250
mV
Output Offset Voltage, VOS
1150
1250
mV
Output Impedance, Single-Ended, RO
80
100
120
Ω
RO Single-Ended Mismatch
10
%
Maximum Clock Rate
625
MHz
1 DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.
2 DCI_P and DCI_N pins, as well as SYNC_IN_P and SYNC_IN_N pins.
3 DCO_P and DCO_N pins, as well as SYNC_OUT_P/SYNC_OUT_N pins with 100 Ω differential termination.


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