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NM27C512N90 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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NM27C512N90 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 10 page 2 www.fairchildsemi.com Connection Diagrams Compatible EPROM pin configurations are shown in the blocks adjacement to the NM27C512 pins. Commercial Temp Range (0 °C to +70°C) Parameter/Order Number Access Time (ns) NM27C512 Q, N, V 90 90 NM27C512 Q, N, V 120 120 NM27C512 Q, N, V 150 150 Industrial Temp Range (-40 °C to +85°C) Parameter/Order Number Access Time (ns) NM27C512 QE, NE, VE 120 120 NM27C512 QE, NE, VE 150 150 Q = Quartz-Windowed Ceramic DIP Package N = Plastic DIP Package V = PLCC Package • All packages conform to the JEDEC standard. • All versions are guaranteed to function for slower speeds. Pin Names A0–A15 Addresses CE/PGM Chip Enable/Program OE Output Enable O0–O7 Outputs NC Don’t Care (During Read) PLCC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND VCC A14 A13 A8 A9 A11 OE/VPP A10 CE/PGM O7 O6 O5 O4 O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC XX/PGM XX A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 VCC XX/PGM A17 A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 VCC A14 A13 A8 A9 A11 OE A10 CE/PGM O7 O6 O5 O4 O3 27C256 27C010 27C020 27C040 27C080 VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE/PGM O7 O6 O5 O4 O3 VCC A18 A17 A14 A13 A8 A9 A11 OE/ VPP A10 CE/PGM O7 O6 O5 O4 O3 27C080 27C040 27C020 27C010 27C256 A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND XX/ VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND XX/ VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND XX/ VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND DIP NM27C512 A8 A9 A11 NC OE/VPP A10 CE/PGM O7 O8 A6 A5 A4 A3 A2 A1 A0 NC O0 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 DS010834-2 DS010834-3 |
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