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NM24C65U Datasheet(PDF) 6 Page - Fairchild Semiconductor

Part No. NM24C65U
Description  64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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www.fairchildsemi.com
NM24C65U Rev. B.1
Write Cycle Timing
ACKNOWLEDGE
Acknowledge is a hardware convention used to indicate success-
ful data transfers. The transmitting device, either master or slave,
will release the bus after transmitting eight bits. During the ninth
clock cycle the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to
Figure 4.
The NM24C65Uxxx device will always respond with an acknowl-
edge after recognition of a start condition and its slave address. If
Write Cycle Timing (Figure 1)
SDA
SCL
STOP
CONDITION
START
CONDITION
WORD n
8th BIT
ACK
tWR
SCL
DATA STABLE
DATA
CHANGE
SDA
SDA
SCL
START
CONDITION
STOP
CONDITION
DS800012-4
DS800012-5
Data Validity (Figure 2)
Definition of Start and Stop (Figure 3)
DS800012-6
both the device and a WRITE operation have been selected, the
NM24C65Uxxx will respond with an acknowledge after the receipt
of each subsequent eight bit word.
In the READ mode the NM24C65Uxxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM
RECEIVER
18
9
START
ACKNOWLEDGE
Acknowledge Response from Receiver (Figure 4)
DS800012-7




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