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NM24C65U Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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NM24C65U Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 11 page 5 www.fairchildsemi.com NM24C65U Rev. B.1 BACKGROUND INFORMATION (IIC Bus) As mentioned, the IIC bus allows synchronous bidirectional commu- nication between Transmitter/Receiver using the SCL (clock) and SDA (Data I/O) lines. All communication must be started with a valid START condition, concluded with a STOP condition and acknowl- edged by the Receiver with an ACKNOWLEDGE condition. In addition, since the IIC bus is designed to support other devices such as RAM, EPROM, etc., the device type identifier string, or slave address, must follow the START condition. For EEPROMs, the first 4-bits of the slave address is '1010'. This is then followed by the device selection bits A2, A1 and A0.The final bit in the slave address determines the type of operation performed (READ/ WRITE). A "1" signifies a READ while a "0" signifies a WRITE. The slave address is then followed by two bytes that define the word address, which is then followed by the data byte. The EEPROMs on the IIC bus may be configured in any manner required, providing the total memory addressed does not exceed 4M bits in the Extended IIC protocol. EEPROM memory address- ing is controlled by hardware configuring the A2, A1, and A0 pins (Device Address pins) with pull-up or pull-down resistors. ALL UNUSED PINS MUST BE GROUNDED (tied to V SS). Addressing an EEPROM memory location involves sending a command string with the following information: [DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD- DRESS]-[BYTE ADDRESS] Definitions Word 8 bits (byte) of data Page 32 sequential addresses (one byte each) that may be programmed during a "Page Write" programming cycle. Master Any IIC device CONTROLLING the transfer of data (such as a microcontroller). Slave Device being controlled (EEPROMS are always considered Slaves). Transmitter Device currently SENDING data on the bus (may be either a Master or Slave). Receiver Device currently RECEIVING data on the bus (Master or Slave). Pin Description SERIAL CLOCK (SCL) The SCL input is used to clock all data into and out of the device. SERIAL DATA (SDA) SDA is a biderectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. Device Address Inputs (A0, A1, A2) Device address pins A0, A1, and A2 are connected to V CC or VSS to configure the EEPROM address for multiple device configuration. A total of eight different devices can be attached to the same SDA bus. Write Protection (WP) If WP is tied to V CC, program WRITE operations onto the upper half of the memory will not be executed. READ operations are always available. If WP is tied to VSS, normal memory operation is enabled, READ/ WRITE over the entire bit memory array. This feature allows the user to assign the upper half of the memory as ROM which can be protected against accidental programming writes. When WRITE is disabled, slave address and word address will be acknowledged but data will not be acknowledged. Device Operation The NM24C65Uxxx supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving devices as the receiver. The device controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. There- fore, the NM24C65Uxxx is considered a slave in all applications. CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH and reserved for indicating start and stop conditions. Refer to Figures 2 and 3. START CONDITION All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The NM24C65Uxxx continuouslymonitorstheSDAandSCLlinesforthestartconditionand will not respond to any command until this condition has been met. STOP CONDITION All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the NM24C65Uxxx to place the device in the standby power mode. ;; SCL SDA IN SDA OUT tF tLOW tHIGH tR tLOW tAA tDH tBUF tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO DS800012-3 Bus Timing |
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