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NM24C65 Datasheet(PDF) 6 Page - Fairchild Semiconductor |
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NM24C65 Datasheet(HTML) 6 Page - Fairchild Semiconductor |
6 / 11 page 6 www.fairchildsemi.com NM24C65 Rev. C.3 Write Cycle Timing ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 4. The NM24C65xxx device will always respond with an acknowl- edge after recognition of a start condition and its slave address. If Write Cycle Timing (Figure 1) SDA SCL STOP CONDITION START CONDITION WORD n 8th BIT ACK tWR SDA SCL DATA STABLE DATA CHANGE SDA SCL START BIT STOP BIT DS500042-4 DS500042-5 Data Validity (Figure 2) Definition of Start and Stop (Figure 3) DS500042-6 both the device and a WRITE operation have been selected, the NM24C65xxx will respond with an acknowledge after the receipt of each subsequent eight bit word. In the READ mode the NM24C65xxx slave will transmit eight bits of data, release the SDA line and monitor the line for an acknowl- edge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode. SCL FROM MASTER Data Output from Transmitter Data Output from Receiver START Acknowledge 18 9 Acknowledge Response from Receiver (Figure 4) DS500042-7 |
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