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NM24C65 Datasheet(PDF) 4 Page - Fairchild Semiconductor

Part No. NM24C65
Description  64K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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www.fairchildsemi.com
NM24C65 Rev. C.3
AC Conditions of Test
Input Pulse Levels
V
CC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10 ns
Input & Output Timing Levels
VCC x 0.5
Output Load
1 TTL Gate and C
L = 100 pF
Read and Write Cycle Limits (Standard and Low V
CC Range - 2.7V-5.5V)
Symbol
Parameter
100 KHz
400 KHz
Units
Min
Max
Min
Max
fSCL
SCL Clock Frequency
100
400
KHz
T
I
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
100
50
ns
Pulse width)
tAA
SCL Low to SDA Data Out Valid
0.3
3.5
0.1
0.9
µs
t
BUF
Time the Bus Must Be Free before
4.7
1.3
µs
a New Transmission Can Start
t
HD:STA
Start Condition Hold Time
4.0
0.6
µs
t
LOW
Clock Low Period
4.7
1.5
µs
tHIGH
Clock High Period
4.0
0.6
µs
t
SU:STA
Start Condition Setup Time
4.7
0.6
µs
(for a Repeated Start Condition)
t
HD:DAT
Data in Hold Time
0
0
ns
t
SU:DAT
Data in Setup Time
250
100
ns
tR
SDA and SCL Rise Time
1
0.3
µs
t
F
SDA and SCL Fall Time
300
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
0.6
µs
tDH
Data Out Hold Time
300
50
ns
t
WR
Write Cycle Time - NM24C65
10
10
ms
(Note 3)
- NM24C65L, NM24C65LZ
15
15
Note 3: The write cycle time (t
WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C65 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address




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