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HEF4093BT Datasheet(PDF) 6 Page - NXP Semiconductors |
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HEF4093BT Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 15 page HEF4093B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 — 21 November 2011 6 of 15 NXP Semiconductors HEF4093B Quad 2-input NAND Schmitt trigger 12. Waveforms Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. tr, tf = input rise and fall times. Fig 4. Propagation delay and output transition time 001aag197 input output tPLH tPHL 0 V VI VM VM VOH VOL tTLH tTHL 90 % 10 % 10 % 90 % tr tf Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD Test data given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 5. Test circuit VDD VI VO 001aag182 DUT CL RT G Table 10. Test data Supply voltage Input Load VDD VI tr, tf CL 5 V to 15 V VSS or VDD 20 ns 50 pF |
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