1. DESCRIPTION

S2S65A30 Data Sheet

Seiko Epson Corporation

1

(Rev.1.0)

1. DESCRIPTION

The S2S65A30 is an image controller IC with additional convenient features and enhanced functions compared

to the conventional IC S2S65A00. In addition to these conventional functions, it has an input image-correction

function achieved by real-time image processing, an Interlace/Progressive conversion function that allows easy

interlace camera connection, a replay function of recorded images and a high-speed write function to a SD card.

The operating-temperature accuracy guarantees -40

°C to +85°C. Compatible with conventional IC pins, the

software is also upper-compatible with the S2S65A00. It is an optimum controller IC for image recording drive

recorders.

1.1 Features

One-chip solution, which can reduce system cost.

Provides JPEG encoding by using 30 fps @VGA hardware (ISO 10918 compliant).

Up to two camera modules can be connected.

Each camera module has two hardware JPEG encoders.

Provides moving-object detection function to support motion detection.

Supports I

Has a CompactFlash interface for a CF memory card or a wireless LAN interface (802.11b).

An SD memory interface for SD memory card connection.

ARM720T 50MHz operation.

USB 2.0 device (High-Speed) function support, which enables connection to a PC.

Supports 8-ch ADC for connection with various analog sensors.

Contains event counter timers.

Memory bus: 2 ports (6bit-Bus: FROM/SRAM, 16/32bit-Bus: SDRAM).

Interlaced/Progressive converion

JPEG decoding

Image light and shade correction

1.2 Built-In Functions

CPU:

32-bit RISC ARM720T (maximum of 56MHz).

32-bit long command codes and 16-bit long command codes called Efficient Thumb Code can be used by

switching them.

32-bit general purpose register (

×31).

A multiplier is included in the CPU.

RAM:

56 KB Built-in RAM for CPU/JPEG Work (CPU Work: 32KB Max.).

Standby Function

A HALT function to stop the CPU clock when any CPU operation is not required.

An I/O clock stop function to stop each clock of the main I/O blocks.

Camera Input/JPEG Encoder:

8-bit parallel interface

× 2 ports

2 camera modules can be connected.

Up to 640

×480 resolution (VGA, QVGA, CIF, QCIF).

Hardware JPEG encoder

× 2

Throughput greater than 30 fps @VGA (when 1 camera module connected).

YUV4-2-2 progressive (both ports)

Pixel clock frequency for inputting camera data is less than 2/3 of CPU clock frequency.

Support of Interlaced signal by Interlace/Progressive conversion(Camera I/F 2ch)