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ADS1271IPWR Datasheet(PDF) 6 Page - Texas Instruments

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Part # ADS1271IPWR
Description  24-Bit, Wide Bandwidth Analog-to-Dogotal Converter
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS1271IPWR Datasheet(HTML) 6 Page - Texas Instruments

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ADS1271
SBAS306F − NOVEMBER 2004 − REVISED OCTOBER 2007
www.ti.com
6
TIMING CHARACTERISTICS: SPI FORMAT
CLK
t
CPW
t
CLK
t
CPW
t
SD
t
S
t
DIST
t
DOHD
t
SPW
Bit 23 (MSB)
Bit 22
Bit 21
t
SPW
t
DOPD
t
CD
t
DS
t
DDO
t
DIHD
••
t
CONV
DRDY
SCLK
DOUT
DIN
TIMING REQUIREMENTS: SPI FORMAT
For TA = −40°C to +105°C and DVDD = 1.65V to 3.6V.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
tCLK
CLK period (1/fCLK)
37
10,000
ns
tCPW
CLK positive or negative pulse width
15
ns
High-Speed mode
256
CLK periods
tCONV
Conversion period (1/fDATA)
High-Resolution mode
512
CLK periods
tCONV
Conversion period (1/fDATA)
Low-Power mode
512
CLK periods
tCD(1)
Falling edge of CLK to falling edge of DRDY
8
ns
tDS(1)
Falling edge of DRDY to rising edge of first SCLK to retrieve data
5
ns
tDDO(1)
Valid DOUT to falling edge of DRDY
0
ns
tSD(1)
Falling edge of SCLK to rising edge of DRDY
8
ns
tS(2)
SCLK period
tCLK
ns
tSPW
SCLK positive or negative pulse width
12
ns
tDOHD(1)(3) SCLK falling edge to old DOUT invalid (hold time)
5
ns
tDOPD(1)
SCLK falling edge to new DOUT valid (propagation delay)
12
ns
tDIST
New DIN valid to falling edge of SCLK (setup time)
6
ns
tDIHD(3)
Old DIN valid to falling edge of SCLK (hold time)
6
ns
(1) Load on DRDY and DOUT = 20pF.
(2) For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc.
(3) tDOHD (DOUT hold time) and tDIHD (DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient
temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.


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