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ADS58B18IRGZR Datasheet(PDF) 1 Page - Texas Instruments |
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ADS58B18IRGZR Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 69 page  ADS58B18 ADS58B19 www.ti.com SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011 11-Bit, 200MSPS/9-Bit, 250MSPS, Ultralow-Power ADCs with Analog Buffer Check for Samples: ADS58B18, ADS58B19 1 FEATURES DESCRIPTION 23 • ADS58B18: 11-Bit, 200MSPS The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) • ADS58B19: 9-Bit, 250MSPS family that features integrated analog buffers and • Integrated High-Impedance Analog Input SNRBoost technology. The ADS58B18 and Buffer ADS58B19 are 11-bit and 9-bit ADCs with sampling • Ultralow Power: rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve – Analog Power: 258mW at 200MSPS high dynamic performance while consuming – I/O Power: 69mW (DDR LVDS, low LVDS extremely low power. The analog input pins have swing) buffers with constant performance and input • High Dynamic Performance: impedance across a wide frequency range. This architecture makes these parts well-suited for – ADS58B18: 66dBFS SNR and 81dBc SFDR multi-carrier, wide bandwidth communications at 150MHz applications such as PA linearization. – ADS58B19: 55.7dBFS SNR and 76dBc The ADS58B18 uses TI-proprietary SNRBoost SFDR at 150MHz technology that can be used to overcome SNR • Enhanced SNR Using TI-Proprietary SNRBoost limitation as a result of quantization noise for Technology (ADS58B18 Only) bandwidths less than Nyquist (fS/2). – –77.7dBFS SNR in 20MHz Bandwidth Both devices have gain options that can be used to • Dynamic Power Scaling with Sample Rate improve SFDR performance at lower full-scale input • Output Interface: ranges, especially at very high input frequencies. They also include a dc offset correction loop that can – Double Data Rate (DDR) LVDS with be used to cancel the ADC offset. At lower sampling Programmable Swing and Strength rates, the ADC automatically operates at scaled-down – Standard Swing: 350mV power with no loss in performance. – Low Swing: 200mV These devices support both double data rate (DDR) – Default Strength: 100Ω Termination low-voltage differential signaling (LVDS) and parallel – 2x Strength: 50Ω Termination CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes – 1.8V Parallel CMOS Interface Also it possible to use low-cost field-programmable gate Supported array (FPGA)-based receivers. They have a • Programmable Gain for SNR/SFDR Trade-Off low-swing LVDS mode that can be used to further • DC Offset Correction reduce the power consumption. The strength of the LVDS output buffers can also be increased to support • Supports Low Input Clock Amplitude 50 Ω differential termination. • Package: QFN-48 (7mm × 7mm) The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range ( –40°C to +85°C). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 PowerPAD is a trademark of Texas Instruments Incorporated. 3 All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. © 2009–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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