TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I

VOICE-BAND ANALOG INTERFACE CIRCUITS

SLAS017F − MARCH 1988 − REVISED MAY 1995

11

POST OFFICE BOX 655303

explanation of internal timing configuration (continued)

If the transmit and receive sections are configured to be synchronous (see WORD/BYTE description), then both

the low-pass and bandpass switched-capacitor filter clocks are derived from TX counter A. Also, both the D/A

and A/D conversion timing are derived from the TX counter A and TX counter B. When the transmit and receive

sections are configured to be synchronous, the RX counter A, RX counter B, RA register, RA’ register, and RB

registers are not used.

AIC DR or DX word bit pattern

d14

d13

d12

d11

d10

d9

d8

d7

d6

d5

d4

d3

d2

d1

d0

d15

A/D or D/A MSB,

1st bit sent

1st bit sent of 2nd byte

A/D or D/A LSB

AIC DX data word format section

d15

d14

d13

d12

d11

d10

d9

d8

d7

d6

d5

d4

d3

d2

d1

d0

Comments

primary DX serial communication protocol

←d15 (MSB) through d2 go to the D/A converter register

→

0

0

The TX and RX counter As are loaded with the TA

and RA register values. The TX and RX counter Bs

are loaded with TB and RB register values.

←d15 (MSB) through d2 go to the D/A converter register

→

0

1

The TX and RX counter As are loaded with the TA +

TA’ and RA + RA’ register values. The TX and RX

counter Bs are loaded with the TB and RB register

values. LSBs d1 = 0 and d0 =1 cause the next D/A

and A/D conversion periods to be changed by the

addition of TA’ and RA’ master clock cycles, in which

TA’ and RA’ can be positive or negative or zero (refer

to Table 1).

←d15 (MSB) through d2 go to the D/A converter register

→

1

0

The TX and RX counter As are loaded with the TA −

TA’ and RA − RA’ register values. The TX and RX

counter Bs are loaded with the TB and RB register

values. LSBs d1 = 1 and d0 = 0 cause the next D/A

and A/D conversion periods to be changed by the

subtraction of TA’ and RA’ master clock cycles, in

which TA’ and RA’ can be positive or negative or zero

(refer to Table 1).

←d15 (MSB) through d2 go to the D/A converter register

→

1

1

The TX and RX counter As are loaded with the TA

and RA register converter register values. The TX

and RX counter Bs are loaded with the TB and RB

register values. After a delay of four shift clock

cycles, a secondary transmission immediately

follows to program the AIC to operate in the desired

configuration.

NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (primary communications) to the AIC initiates

secondary communications upon completion of the primary communications. Upon completion of the primary communication, FSX

remains high for four shift clock cycles and then goes low and initiates the secondary communication. The timing specifications for the

primary and secondary communications are identical. In this manner, the secondary communication, if initiated, is interleaved between

successive primary communications. This interleaving prevents the secondary communication from interfering with the primary

communications and DAC timing, thus preventing the AIC from skipping a DAC output. In the synchronous mode, FSR is not asserted

during secondary communications.