NCP5911

http://onsemi.com

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APPLICATION INFORMATION

The NCP5911 gate driver is a single phase MOSFET

driver designed for driving N−channel MOSFETs in a

synchronous buck converter topology. The NCP5911 is

designed to work with ON Semiconductor’s NCP6131

multi−phase controller. This gate driver is optimized for

notebook applications.

Undervoltage Lockout

during startup. The PWM signal will control the gate status

Three−State EN Signal

Undervoltage Lockout will de−assert the EN pin, which

will pull down the DRON pin of the controller as well.

When EN is set to the mid state, both DRVH and DRVL

are set low, to force diode mode operation.

PWM Input and Zero Cross Detect (ZCD)

The PWM input, along with EN and ZCD, control the state

of DRVH and DRVL.

When PWM is set high, DRVH will be set high after the

adaptive non−overlap delay. When PWM is set low, DRVL

will be set high after the adaptive non−overlap delay.

When PWM is set to the mid state, DRVH will be set low,

and after the adaptive non−overlap delay, DRVL will be set

high. DRVL remains high during the ZCD blanking time.

When the timer has expired, the SW pin will be monitored

for zero cross detection. After the detection, DRVL will be

set low.

Adaptive Non−overlap

Adaptive dead time control is used to avoid shoot−through

damage of the power MOSFETs. When the PWM signal

pulls high, DRVL will be set low and the driver will monitor

the gate voltage of the low side MOSFET. When the DRVL

voltage falls below the gate threshold, DRVH will be set to

driver will monitor the gate voltage of the high side

MOSFET. When the DRVH−SWN voltage falls below the

top gate drive threshold, DRVL will be set to high after the

Layout Guidelines

The layout for a DC−DC converter is very important. The

to the driver IC.

Connect the GND pin to a local ground plane. The ground

plane can provide a good return path for gate drives and

reduce the ground noise. The thermal slug should be tied to

the ground plane for good heat dissipation. To minimize the

ground loop for the low side MOSFET, the driver GND pin

should be close to the low−side MOSFET source pin. The

gate drive trace should be routed to minimize its length. The

minimum width is 20 mils.

Gate Driver Power Loss Calculation

The gate driver power loss consists of the gate drive loss

and quiescent power loss.

The equation below can be used to calculate the power

each synchronous MOSFET.

(eq. 1)

2

n

of the driver.