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ADV7123KSTZ140 Datasheet(PDF) 7 Page - Analog Devices |
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ADV7123KSTZ140 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 24 page  ADV7123 Rev. D | Page 7 of 24 Parameter Min Typ Max Unit Total Harmonic Distortion fCLK = 50 MHz; fOUT = 1.00 MHz TA = 25°C 66 dBc TMIN to TMAX 65 dBc fCLK = 50 MHz; fOUT = 2.00 MHz 64 dBc fCLK = 100 MHz; fOUT = 2.00 MHz 64 dBc fCLK = 140 MHz; fOUT = 2.00 MHz 55 dBc DAC PERFORMANCE Glitch Impulse 10 pV-sec DAC-to-DAC Crosstalk3 23 dB Data Feedthrough4, 5 22 dB Clock Feedthrough4, 5 33 dB 1 These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range. 2 Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF. 3 DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions. 4 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. 5 TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs. 5 V TIMING SPECIFICATIONS VAA = 5 V ± 5%,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C. Table 5. Parameter3 Symbol Min Typ Max Unit Conditions ANALOG OUTPUTS Analog Output Delay t6 5.5 ns Analog Output Rise/Fall Time4 t7 1.0 ns Analog Output Transition Time5 t8 15 ns Analog Output Skew6 t9 1 2 ns CLOCK CONTROL CLOCK Frequency7 fCLK 0.5 50 MHz 50 MHz grade 0.5 140 MHz 140 MHz grade 0.5 240 MHz 240 MHz grade Data and Control Setup t1 0.5 ns Data and Control Hold t2 1.5 ns CLOCK Period t3 4.17 ns CLOCK Pulse Width High t4 1.875 ns fCLK_MAX = 240 MHz CLOCK Pulse Width Low t5 1.875 ns fCLK_MAX = 240 MHz CLOCK Pulse Width High t4 2.85 ns fCLK_MAX = 140 MHz CLOCK Pulse Width Low t5 2.85 ns fCLK_MAX = 140 MHz CLOCK Pulse Width High t4 8.0 ns fCLK_MAX = 50 MHz CLOCK Pulse Width Low t5 8.0 ns fCLK_MAX = 50 MHz Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles PSAVE Up Time6 t10 2 10 ns 1 These maximum and minimum specifications are guaranteed over this range. 2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization. |
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