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TMS320C6748BZCEA3 Datasheet(PDF) 7 Page - Texas Instruments |
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TMS320C6748BZCEA3 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 273 page  TMS320C6748 www.ti.com SPRS590E – JUNE 2009 – REVISED AUGUST 2013 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the changes made to the SPRS590D device-specific data manual to make it an SPRS590E revision. Revision History SEE ADDITIONS/MODIFICATIONS/DELETIONS Updated/Changed “C6-Integra” to “C6000” Updated/Changed "DDR2/mDDR Controller" to "DDR2/mDDR Memory Controller" Updated/Changed the DDR2 SDRAM from "512 MB" to "256MB", where applicable Updated/Changed instances of "LCD_CLK (SYSCLK)" to "LCD_MCLK" Global Updated/Changed instances of "MDIO_CLK" to "MDCLK" Updated/Changed instances of "MDIO_D" to "MDIO" Updated/Changed Features, Application and Description sections. Deleted "Parameter" header title from Timing Requirement tables. Updated/Changed the "16-Bit DDR2 SDRAM With 512 MB Address Space" bullet to "16-Bit Section 1.1 DDR2 SDRAM With 256 MB Address Space" Features Deleted Highlights section. Information was duplicated elsewhere in Features. Section 1.2 Added Applications section. Applications Figure 1-1, C6748 Functional Block Diagram: Section 1.4 Functional Block Diagram • Added "Memory Protection" in the System Control Block Table 2-1, Characteristics of the C6748: Section 2.1 • Updated/Changed the JTAG RSDL_ID from "0x0B7D_102F" [silicon revision 1.x only] to " Device Characteristics see Section 5.34.4.1, JTAG Peripheral Register Description" Added "Note: Read/Write accesses ..." sentence Table 2-4, C6748 Top Level Memory Map: • Updated/Changed “DDR2 Data” to “DDR2/mDDR Data” Section 2.4 • Updated/Changed the DDR/mDDR Data from “512M” to “256M” [now 0xC000 0000 through Memory Map Summary 0xCFFF FFFF] • Updated/Changed the reserved row “Start Address” range from 0xE000 0000 to “0xD000 0000” to include the additional 256M • Updated/Changed "DDR2 Control Regs" to "DDR2/mDDR Control Regs" Section 2.7.6, DDR2/mDDR Controller: • Updated/Changed name of section from "DDR2 Controller (DDR2)" to "DDR2/mDDR Section 2.7.6 Controller" DDR2/mDDR Controller Table 2-10, DDR2/mDDR Terminal Functions: • Updated/Changed name of table from "DDR2 Controller (DDR2)" to "DDR2/mDDR Terminal Functions" Section 2.7.17 Table 2-21, Universal Serial Bus (USB) Terminal Functions Universal Serial Bus Modules • Updated/Changed the USB0_VDDA12 pin DESCRIPTION column (USB0, USB1) Table 2-35, Unused DDR2/mDDR Memory Controller Signal Configuration: Section 2.8 • Added footnote beginning with "The DDR2/mDDR input buffers are enabled by default..." to Unused Pin Configurations the Configuration column header. Copyright © 2009–2013, Texas Instruments Incorporated Contents 7 Submit Documentation Feedback Product Folder Links: TMS320C6748 |
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