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DS90UB914ATRHSRQ1 Datasheet(PDF) 3 Page - Texas Instruments |
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DS90UB914ATRHSRQ1 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 68 page  1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 DS90UB913AQ 32-Pin WQFN (Top View) VDDIO DIN[8] DIN[9] DIN[10] DIN[11] DIN[7] DIN[6] VDDCML VDDT VDDPLL PDB DOUT- DOUT+ GPO[1] GPO[0] VDDD DAP = GND DS90UB913A-Q1, DS90UB914A-Q1 www.ti.com SNLS443A – MAY 2013 – REVISED JUNE 2013 DS90UB913A-Q1 Pin Diagram Figure 4. Serializer - DS90UB913A-Q1 — Top View DS90UB913A-Q1 Serializer Pin Descriptions Table 1. Pin Descriptions Pin Name Pin No. I/O, Type Description LVCMOS PARALLEL INTERFACE DIN[0:11] 19,20,21,22, Inputs, LVCMOS Parallel Data Inputs. 23,24,26,27, w/ pull down 29,30,31,32 HSYNC 1 Inputs, LVCMOS Horizontal SYNC Input. w/ pull down VSYNC 2 Inputs, LVCMOS Vertical SYNC Input. w/ pull down PCLK 3 Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register. w/ pull down GENERAL PURPOSE OUTPUT (GPO) GPO[1:0] 16,15 Output, LVCMOS General-purpose output pins can be configured as outputs; used to control and respond to various commands. GPO[1:0] can be configured to be the outputs for input signals coming from GPIO[1:0] pins on the Deserializer or can be configured to be outputs of the local register on the Serializer. GPO[2]/CLKOUT 17 Output, LVCMOS GPO2 pin can be configured to be the output for input signal coming from the GPIO2 pin on the Deserializer or can be configured to be the output of the local register on the Serializer. It can also be configured to be the output clock pin when the DS90UB913A-Q1 device is used in the External Oscillator mode. See Applications Information for a detailed description of the DS90UB913A/914A chipsets working with the external oscillator. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DS90UB913A-Q1 DS90UB914A-Q1 |
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