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DS90UB914ATRHSJQ1 Datasheet(PDF) 7 Page - Texas Instruments |
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DS90UB914ATRHSJQ1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 68 page  DS90UB913A-Q1, DS90UB914A-Q1 www.ti.com SNLS443A – MAY 2013 – REVISED JUNE 2013 Table 2. Pin Descriptions (continued) Pin Name Pin No. I/O, Type Description Inverting Differential input, bidirectional control channel. The IO must be AC coupled Input/Output, RIN1- 33 with a 0.1µF capacitor. For applications using single-ended coaxial interconnect, CML terminate to Ground with a 0.047µF capacitor. RES 43,44 — Reserved. This pin must always be tied low. CMLOUTP/N 38,39 Route to test point or leave open if unused. POWER AND GROUND LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered VDDIO1/2/3 29, 20, 7 Power, Digital from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%. VDDD 17 Power, Digital Digital Core Power, 1.8V ±5%. VDDSSCG 3 Power, Analog SSCG PLL Power, 1.8V ±5%. VDDR 36 Power, Analog Rx Analog Power, 1.8V ±5%. VDDCML0/1 40,31 Power, Analog CML and Bidirectional control channel Drive Power, 1.8V±5%. VDDPLL 45 Power, Analog PLL Power, 1.8V ±5%. DAP must be grounded. DAP is the large metal contact at the bottom side, located at VSS DAP Ground, DAP the center of the WQFN package. Connected to the ground plane (GND) with at least 16 vias. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DS90UB913A-Q1 DS90UB914A-Q1 |
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