AD9640-125EBZ datasheet(10/52 Pages) AD

Part #	AD9640-125EBZ

Description	14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter

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AD9640

Rev. B | Page 10 of 52

Parameter

Temperature

Min

Typ

Max

Unit

DIGITAL OUTPUTS

CMOS Mode—DRVDD = 3.3 V

High Level Output Voltage (IOH = 50 μA)

Full

3.29

V

High Level Output Voltage (IOH = 0.5 mA)

Full

3.25

V

Low Level Output Voltage (IOL = 1.6 mA)

Full

0.2

V

Low Level Output Voltage (IOL = 50 μA)

Full

0.05

V

CMOS Mode—DRVDD = 1.8 V

High Level Output Voltage (IOH = 50 μA)

Full

1.79

V

High Level Output Voltage (IOH = 0.5 mA)

Full

1.75

V

Low Level Output Voltage (IOL = 1.6 mA)

Full

0.2

V

Low Level Output Voltage (IOL = 50 μA)

Full

0.05

V

LVDS Mode—DRVDD = 1.8 V

Differential Output Voltage (VOD), ANSI Mode

Full

250

350

450

mV

Output Offset Voltage (VOS), ANSI Mode

Full

1.15

1.25

1.35

V

Differential Output Voltage (VOD), Reduced Swing Mode

Full

150

200

280

mV

Output Offset Voltage (VOS), Reduced Swing Mode

Full

1.15

1.25

1.35

V

1 Pull up.

2 Pull down.

SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND

AD9640BCPZ-105

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,

DCS enabled, unless otherwise noted.

Table 6.

Parameter

Temp

AD9640ABCPZ-80

AD9640BCPZ-80

AD9640ABCPZ-105/

AD9640BCPZ-105

Unit

Min

Typ

Max

Min

Typ

Max

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

625

MHz

Conversion Rate

DCS Enabled1

Full

20

80

20

105

MSPS

DCS Disabled1

Full

10

80

10

105

MSPS

CLK Period—Divide by 1 Mode (tCLK)

Full

12.5

9.5

ns

CLK Pulse Width High

Divide by 1 Mode, DCS Enabled

Full

3.75

6.25

8.75

2.85

4.75

6.65

ns

Divide by 1 Mode, DCS Disabled

Full

5.63

6.25

6.88

4.28

4.75

5.23

ns

Divide by 2 Mode, DCS Enabled

Full

1.6

ns

Divide by 3 Through 8, DCS Enabled

Full

0.8

ns

DATA OUTPUT PARAMETERS (DATA, FD)

CMOS Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD)2

Full

2.2

4.5

6.4

2.2

4.5

6.4

ns

DCO Propagation Delay (tDCO)

Full

3.8

5.0

6.8

3.8

5.0

6.8

ns

Setup Time (tS)

Full

6.25

5.25

ns

Hold Time (tH)

Full

5.75

4.25

ns

CMOS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2

Full

2.4

5.2

6.9

2.4

5.2

6.9

ns

DCO Propagation Delay (tDCO)

Full

4.0

5.6

7.3

4.0

5.6

7.3

ns

LVDS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2

Full

3.0

3.7

4.4

3.0

3.7

4.4

ns

DCO Propagation Delay (tDCO)

Full

5.4

7.0

8.4

5.2

6.4

7.6

ns

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