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AT45DB161E-SFH-Y Datasheet(PDF) 8 Page - ATMEL Corporation |
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AT45DB161E-SFH-Y Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 70 page  8 Atmel AT45DB161E [PRELIMINARY DATASHEET] 8782A–DFLASH–3/12 A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.3 Continuous Array Read (High Frequency Mode: 0Bh Opcode) This command can be used with the serial interface to read the Main Memory Array sequentially in High-Speed mode for any clock frequency up to the maximum specified by fCAR1. To perform a Continuous Read Array with the standard DataFlash page size (528 bytes), the CS must first be asserted then an opcode 0Bh must be clocked into the device followed by three address bytes and one dummy byte. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page of the Main Memory Array to read and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the page. To perform a Continuous Read with the binary page size (512 bytes), the opcode 0Bh must be clocked into the device followed by three address bytes (A20 - A0) and one dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the Main Memory Array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.4 Continuous Array Read (Low Frequency Mode: 03h Opcode) This command can be used with the serial interface to read the Main Memory Array sequentially without dummy bytes up to maximum frequencies specified by fCAR2. To perform a Continuous Read Array with the standard DataFlash page size (528 bytes), the CS must first be asserted then an opcode 03h must be clocked into the device followed by three address bytes. The first 12 bits (PA11 - PA0) of the 22 bit address sequence specify which page of the Main Memory Array to read and the last 10 bits (BA9 - BA0) of the 22 bit address sequence specify the starting byte address within the page. To perform a Continuous Read with the binary page size (512 bytes), the opcode 03h must be clocked into the device followed by three address bytes (A20 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO pin. The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the Main Memory Array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR2 specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.5 Continuous Array Read (Low Power Mode: 01h Opcode) This command is ideal for applications that want to minimize power consumption and do not need to read the memory array at high frequencies. The command allows reading the main memory array sequentially without dummy bytes up to maximum frequencies specified by fCAR3. To perform a Continuous Read Array with the standard DataFlash page size (528 bytes), the CS must first be asserted then an opcode 01h must be clocked into the device followed by three address bytes. The first 12 bits (PA11 - PA0) of the 22 bit address sequence specify which page of the Main Memory Array to read and the last 10 bits (BA9 - BA0) of the 22 bit address sequence specify the starting byte address within the page. To perform a Continuous Read with the binary page size (512 bytes), the opcode 01h must be clocked into the device |
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