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AT45DB161E-CCDU-T Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT45DB161E-CCDU-T Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 70 page  7 Atmel AT45DB161E [PRELIMINARY DATASHEET] 8782A–DFLASH–3/12 5. Read Commands By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please see Section 25. Detailed Bit-level Read Waveforms: Atmel RapidS Mode 0/Mode 3 diagrams in this datasheet for details on the clock cycle sequences for each mode. 5.1 Continuous Array Read (Legacy Command: E8h Opcode) By supplying an initial starting address for the Main Memory Array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one Continuous Read operation without the need of additional address sequenced. To perform a Continuous Read from the standard DataFlash page size (528 bytes), an opcode of E8h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four dummy bytes. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page of the Main Memory Array to read and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the page. To perform a Continuous Read from the binary page size (512 bytes), an opcode of E8h must be clocked into the device followed by three address bytes and four dummy bytes. The first 12 bits (A20 - A9) of the 21-bit sequence specify which page of the Main Memory Array to read and the last nine bits (A8 - A0) of the 21-bit address sequence specify the starting byte address within the page. The dummy bytes that follow the address bytes are needed to initialize the read operation. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the Main Memory Array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses the data buffers and leaves the contents of the buffers unchanged. Note: This command is not recommended for new designs. 5.2 Continuous Array Read (High Frequency Mode: 1Bh Opcode) This command can be used with the serial interface to read the Main Memory Array sequentially in very High-Speed (HS) mode for any clock frequency up to the maximum specified by fCAR1. To perform a Continuous Read Array with the standard DataFlash page size (528 bytes), the CS must first be asserted then an opcode 1Bh must be clocked into the device followed by three address bytes and two dummy bytes. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page of the Main Memory Array to read and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the page. To perform a Continuous Read with the binary page size (512 bytes), the opcode 1Bh must be clocked into the device followed by three address bytes (A20 - A0) and two dummy bytes. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO (Serial Output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the Main Memory Array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. |
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