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AT45DB161E-MDH-B Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT45DB161E-MDH-B Datasheet(HTML) 9 Page - ATMEL Corporation |
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9 / 70 page  9 Atmel AT45DB161E [PRELIMINARY DATASHEET] 8782A–DFLASH–3/12 followed by three address bytes (A20 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO pin. The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the Main Memory Array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR3 specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.6 Main Memory Page Read A Main Memory Page Read allows the user to read data directly from any one of the 4,096 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read using the standard DataFlash page size (528 bytes), an opcode of D2h must be clocked into the device followed by three address bytes (which comprise the 24 bit page and byte address sequence) and four dummy bytes. The first 12 bits (PA11 - PA0) of the 22 bit address sequence specify the page in main memory to be read and the last 10 bits (BA9 - BA0) of the 22 bit address sequence specify the starting byte address within that page. To start a page read using the binary page size (512 bytes), the opcode D2h must be clocked into the device followed by three address bytes and four dummy bytes. The first 12 bits (A20 - A9) of the 21 bits address sequence specify which page of the Main Memory Array to read, and the last nine bits (A8 - A0) of the 21 bits address sequence specify the starting byte address within that page. The dummy bytes that follow the address bytes are sent to initialize the read operation. Following the dummy bytes, the additional pulses on SCK result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. When the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Main Memory Page Read is defined by the fSCK specification. The Main Memory Page Read bypasses both data buffers and leaves the contents of the buffers unchanged. 5.7 Buffer Read The SRAM data buffers can be accessed independently from the Main Memory Array and utilizing the Buffer Read command allows data to be sequentially read directly from the buffers. Four opcodes, D4h or D1h for Buffer 1 and D6h or D3h for Buffer 2, can be used for the Buffer Read command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the buffer. The D4h and D6h opcode can be used at any SCK frequency up to the maximum specified by fCAR1. While the D1h and D3h opcode can be used for lower frequency read operations up to the maximum specified by fCAR2. To perform a Buffer Read using the standard DataFlash buffer size (528 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 14 dummy bits and 10 buffer address bits (BFA9 - BFA0). To perform a Buffer Read using the binary buffer size (512 bytes), the opcode must be clocked into the device followed by three address bytes comprised of 15 dummy bits and nine buffer address bits (BFA8 - BFA0). Following the address bytes, one dummy bytes must be clocked in to initialize the read operation if using opcodes D4h or D6h. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). |
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