Electronic Components Datasheet Search |
|
AD7880BR Datasheet(PDF) 5 Page - Analog Devices |
|
AD7880BR Datasheet(HTML) 5 Page - Analog Devices |
5 / 16 page AD7880 REV. 0 –5– + – R V INA V INB R V DAC Figure 4. AD7880 Input Circuit The AD7880 accommodates three separate input ranges, 0 to VREF, 0 to 2 VREF and ±V REF. The input configurations corre- sponding to these ranges are shown in Figures 5, 6 and 7. With VREF = VDD and using a nominal VDD of +5 V, the input ranges are 0 V to 5 V, 0 V to 10 V and +5 V, as shown in Table II. Table II. Analog Input Ranges Analog Input Input Connections Connection Range VREF VINA VINB Diagram 0 V to +5 V VDD VIN VIN Figure 5 0 V to +10 V VDD VIN AGND Figure 6 ±5 V VDD VIN VREF Figure 7 + – R R SAMPLING COMPARATOR V INA V INB V REF AGND 12-BIT DAC 0 TO V REF V REF = 0 TO V REF V IN Figure 5. 0 to VREF Unipolar Input Configuration + – R R SAMPLING COMPARATOR V INA V INB V REF AGND 12-BIT DAC 0 TO V REF V REF = 0 TO 2V REF V IN Figure 6. 0 to 2 VREF Unipolar Input Configuration + – R R SAMPLING COMPARATOR V INA V INB V REF AGND 12-BIT DAC 0 TO V REF V REF = V REF V IN ± Figure 7. ±V REF Bipolar Input Configuration CIRCUIT INFORMATION The AD7880 is a +5 V single supply 12-bit A/D converter. The part requires no external components apart from a 2.5 MHz ex- ternal clock and power supply decoupling capacitors. It contains a 12-bit successive approximation ADC based on a fast-settling voltage-output DAC, a high speed comparator and SAR, as well as the necessary control logic. The charge balancing comparator used in the AD7880 provides the user with an inherent track- and-hold function. The ADC is specified to work with sampling rates up to 66 kHz. CONVERTER DETAILS The AD7880 conversion cycle is initiated on the rising edge of the CONVST pulse, as shown in the timing diagram of Figure 1. The rising edge of the CONVST pulse places the track/hold amplifier into “HOLD” mode. The conversion cycle then takes between 26 and 28 clock periods. The maximum specified con- version time is 12 µs. This corresponds to a conversion cycle time of 28 clock periods with a CLKIN frequency of 2.5 MHz and also includes internal propagation delays. During conver- sion the BUSY output will remain low, and the output databus drivers will be three-stated. When a conversion is completed, the BUSY output will go to a high level, and the result of the conversion can be read by bringing CS and RD low. The track/hold amplifier acquires a 12-bit input signal in 3 µs. The overall throughput time for the AD7880 is equal to the conversion time plus the track/hold acquisition time. For a 2.5 MHz input clock the throughput time is 15 µs. REFERENCE INPUT For specified performance, it is recommended that the reference input be tied to VDD. The part, however, will operate with a ref- erence down to 2.5 V though with reduced performance specifi- cations. Figure 3 shows a graph of signal-to-noise ratio (SNR) versus VREF. VREF must not be allowed to go above VDD by more than 100 mV. 74 72 70 68 66 64 62 60 234 5 V REF – Volts F = 51.2kHz S F = 2.525kHz IN T = 25 C A Figure 3. SNR vs. VREF ANALOG INPUT The AD7880 has two analog input pins, VINA and VINB. Figure 4 shows the input circuitry to the ADC sampling comparator. The on-board attenuator network, made up of equal resistors, allows for various input ranges. |
Similar Part No. - AD7880BR |
|
Similar Description - AD7880BR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |