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LM3485MM Datasheet(PDF) 11 Page - Texas Instruments |
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LM3485MM Datasheet(HTML) 11 Page - Texas Instruments |
11 / 23 page LM3485 www.ti.com SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 Figure 4. Current Sensing by VDS The current limit is activated when the voltage at the ADJ pin exceeds the voltage at the ISENSE pin. The ISENSE comparator triggers the 9µs one shot pulse generator forcing the driver to turn the PFET off. The driver turns the PFET back on after 9µs. If the current has not reduced below the set threshold, the cycle will repeat continuously. A filter capacitor, CADJ, should be placed as shown in Figure 4. CADJ filters unwanted noise so that the ISENSE comparator will not be accidentally triggered. A value of 100pF to 1nF is recommended in most applications. Higher values can be used to create a soft-start function (see START UP). The current limit comparator has approximately 100ns of blanking time. This ensures that the PFET is fully on when the current is sensed. However, under extreme conditions such as cold temperature, some PFETs may not fully turn on within the blanking time. In this case, the current limit threshold must be increased. If the current limit function is used, the on time must be greater than 100ns. Under low duty cycle operation, the maximum operating frequency will be limited by this minimum on time. During current limit operation, the output voltage will drop significantly as will operating frequency. As the load current is reduced, the output will return to the programmed voltage. However, there is a current limit fold back phenomenon inherent in this current limit architecture. See Figure 5. Figure 5. Current Limit Fold Back Phenomenon At high input voltages (>28V) increased undershoot at the switch node can cause an increase in the current limit threshold. To avoid this problem, a low Vf Schottky catch diode must be used (see CATCH DIODE SELECTION (D1)). Additionally, a resistor can be placed between the ISENSE pin and the switch node. Any value up to approximately 600 Ω is recommended. START UP The current limit circuit is active during start-up. During start-up the PFET will stay on until either the current limit or the feedback comparator is tripped If the current limit comparator is tripped first then the fold back characteristic should be taken into account. Start- up into full load may require a higher current limit set point or the load must be applied after start-up. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM3485 |
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