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EP1S60F1508I7ES Datasheet(PDF) 3 Page - Altera Corporation |
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EP1S60F1508I7ES Datasheet(HTML) 3 Page - Altera Corporation |
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3 / 292 page  Altera Corporation iii Contents Chapter Revision Dates .......................................................................... vii About This Handbook .............................................................................. ix How to Find Information ........................................................................................................................ ix How to Contact Altera ............................................................................................................................. ix Typographic Conventions ........................................................................................................................ x Section I. Stratix Device Family Data Sheet Revision History ............................................................................................................................ Part I–1 Chapter 1. Introduction Introduction ............................................................................................................................................ 1–1 Features ................................................................................................................................................... 1–2 Chapter 2. Stratix Architecture Functional Description .......................................................................................................................... 2–1 Logic Array Blocks ................................................................................................................................ 2–3 LAB Interconnects ............................................................................................................................ 2–4 LAB Control Signals ......................................................................................................................... 2–5 Logic Elements ....................................................................................................................................... 2–6 LUT Chain & Register Chain .......................................................................................................... 2–8 addnsub Signal ................................................................................................................................. 2–8 LE Operating Modes ........................................................................................................................ 2–8 Clear & Preset Logic Control ........................................................................................................ 2–13 MultiTrack Interconnect ..................................................................................................................... 2–14 TriMatrix Memory ............................................................................................................................... 2–21 Memory Modes ............................................................................................................................... 2–22 Clear Signals .................................................................................................................................... 2–24 Parity Bit Support ........................................................................................................................... 2–24 Shift Register Support .................................................................................................................... 2–25 Memory Block Size ......................................................................................................................... 2–26 Independent Clock Mode .............................................................................................................. 2–44 Input/Output Clock Mode ........................................................................................................... 2–46 Read/Write Clock Mode ............................................................................................................... 2–49 Single-Port Mode ............................................................................................................................ 2–51 Multiplier Block .............................................................................................................................. 2–57 Adder/Output Blocks ................................................................................................................... 2–61 Modes of Operation ....................................................................................................................... 2–64 |
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