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EP1SGX40FF1020C7N Datasheet(PDF) 6 Page - Altera Corporation |
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EP1SGX40FF1020C7N Datasheet(HTML) 6 Page - Altera Corporation |
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6 / 272 page  1–4 Altera Corporation Stratix GX Device Handbook, Volume 1 February 2005 High-Speed I/O Interface Functional Description High-Speed I/O Interface Functional Description The Stratix GX device family supports high-speed serial transceiver blocks with CDR circuitry as well as source-synchronous interfaces. The channels on the right side of the device use an embedded circuit dedicated for receiving and transmitting high-speed serial data streams to and from the system board. These channels are clustered in a four-channel serial transceiver building block and deliver high-speed bidirectional point-to-point data transmissions to provide up to 3.1875 Gbps of full-duplex data transmission per channel. The channels on the left side of the device support source-synchronous data transfers at up to 1 Gbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure 1–1 shows the Stratix GX I/O blocks. The differential source-synchronous serial interface and the high-speed serial interface are described in the Stratix GX Transceivers chapter of the Stratix GX Device Handbook, Volume 1. EP1SGX25D 455 607 EP1SGX25F 607 EP1SGX40D 624 EP1SGX40G 624 Note to Table 1–2: (1) The number of I/O pins listed for each package includes dedicated clock pins and dedicated fast I/O pins. However, these numbers do not include high-speed or clock reference pins for high-speed I/O standards. Table 1–3. Stratix GX FineLine BGA Package Sizes Dimension 672 Pin 1,020 Pin Pitch (mm) 1.00 1.00 Area (mm2) 729 1,089 Length × width (mm × mm) 27 × 27 33 × 33 Table 1–4. Stratix GX Device Speed Grades Device 672-Pin FineLine BGA 1,020-pin FineLine BGA EP1SGX10 -5, -6, -7 EP1SGX25 -5, -6, -7 -5, -6, -7 EP1SGX40 -5, -6, -7 Table 1–2. Stratix GX Package Options & I/O Pin Counts (Part 2 of 2) Note (1) Device 672-Pin FineLine BGA 1,020-Pin FineLine BGA |
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