Functional Description

Page 5

Configuration Devices for SRAM-Based LUT Devices

January 2012

Altera Corporation

Figure 1 shows the configuration device block diagram.

Stratix II

EP2S15

5,000,000

—

—

—

—

3

EP2S30

10,100,000

—

—

—

—

7

EP2S60

17,100,000

—

———11

EP2S90

27,500,000

—

———17

EP2S130

39,600,000

—

———24

EP2S180

52,400,000

—

———31

Notes to Table 2:

(1) Raw Binary File (.rbf) were used to determine these sizes.

(2) This number is calculated with the Cyclone series compression feature enabled.

(3) EP1S10 ES devices requires four EPC2 devices.

Table 2. Supported Configuration Devices (Part 4 of 4)

Device Family

Device

Data Size (Bits)

(1)

EPC1064 or

EPC1064V

EPC1213

EPC1441

EPC1

EPC2

Figure 1. Configuration Device Block Diagram

Notes to Figure 1:

(1) The EPC1441 devices do not support data cascading. The EPC1, EPC2, and EPC1213 devices support data cascading.

(2) The OE pin is a bidirectional open-drain pin.

DCLK

nCS

OE

Decode

Logic

Address

DATA

DATA

Shift

Register

EPROM

Array

nCS

Decode

Logic

Address

Oscillator

Oscillator

Control

EPROM

Array

Shift

Register

DATA

DATA

DCLK

nCASC

nCASC

(1)

(1)

FPGA (except FLEX 8000) Configuration Using an EPC2, EPC1, or EPC1441

FLEX 8000 Device Configuration Using an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V

Address

Counter

CLK

ENA

nRESET

Error

Detection

Circuitry

OE

Address

Counter

CLK

ENA

nRESET

(2)