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E-GSM900 Datasheet(PDF) 6 Page - Silicon Laboratories

Part No. E-GSM900
Description  Single 8x8 mm package CMOS process technology Intergrated GSM/GPRS transceiver including
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Maker  SILABS [Silicon Laboratories]
Homepage  http://www.silabs.com
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 6 page
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Aero I
6
Rev. 1.0
Table 4. AC Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Cycle Time
tCLK
Figures 1, 3
35
ns
SCLK Rise Time
tR
Figures 1, 3
50
ns
SCLK Fall Time
tF
Figures 1, 3
50
ns
SCLK High Time
tHI
Figures 1, 3
10
ns
SCLK Low Time
tLO
Figures 1, 3
10
ns
PDN Rise Time
tPR
Figure 2
10
ns
PDN Fall Time
tPF
Figure 2
10
ns
SDI Setup Time to SCLK
tSU
Figure 3
15
ns
SDI Hold Time from SCLK
tHOLD
Figure 3
10
ns
SEN
↓ to SCLK↑ Delay Time
tEN1
Figure 3
10
ns
SCLK
↑ to SEN↑ Delay Time
tEN2
Figures 3, 4
12
ns
SEN
↑ to SCLK↑ Delay Time
tEN3
Figures 3, 4
12
ns
SEN Pulse Width1
tW1, tW3
Figures 3, 4
10
ns
DGAIN bits only
130
µs
tW2
Option 2 only
10
ns
SCLK
↓ to SDO Time
tCA
Figure 4
27
ns
Digital Input Pin Capacitance2
——
5
pF
XIN Input Resistance3
RXIN
10
15
20
k
XIN Input Capacitance3
CXIN
710
14
pF
XIN Input Sensitivity3
VREF
0.5
VPP
XIN Input Frequency3,4
fREF
XSEL = 0, DIV2 = 0
13
MHz
XSEL = 1, DIV2 = 1
26
MHz
Notes:
1. Two programming options are allowed for SEN. Either option may be used. In both cases, the SEN pulse width must be
at least 10 ns after writing all registers except after DGAIN is written. After DGAIN is written, SEN must be held high for
at least 130
µs. See “AN50: Aero Transceiver Programming Guide.”
2. For pins SCLK, SDI, SEN, XEN, and PDN.
3. For XIN pin.
4. The XSEL and
DIV2 bits control internal divide-by-two circuits and do not effect the XOUT pin.




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