S1C17M01

Flow meter controller with AFE

■ DESCRIPTIONS

The S1C17M01 is an ultra low-power MCU equipped with an MR (magneto resistive) sensor controller that allows an MR

sensor array optimized for flow measurement (recommended sensor: KG1205-61 manufactured by KOHDEN Co., Ltd.) to be

connected directly. This IC includes an LCD driver to display the flow count and the readouts on the indicator, and the

synchronous serial interface, UART, and I2C interface for wireless communication with a remote meter reading system. This

IC allows measurement of various environmental conditions such as a temperature and humidity measurement using the R/F

converter, and a supply voltage measurement using the supply voltage detection circuit.

FEATURES

Model

S1C17M01

CPU

CPU core

Seiko Epson original 16-bit RISC CPU core S1C17

Other

On-chip debugger

Embedded Flash memory

Capacity

32K bytes (for both instructions and data)

Erase/program count

50 times (min.) *Programming by the debugging tool ICDmini

Security function to protect from reading/programming by ICDmini

Other

On-board programming function using ICDmini

Embedded RAM

Capacity

4K bytes

Embedded display RAM

Capacity

32 bytes

Clock generator (CLG)

System clock source

3 sources (IOSC/OSC1/EXOSC)

System clock frequency

(Operating frequency)

16.3 MHz (max.)

7.37 MHz (typ.) embedded oscillator

IOSC oscillator circuit

(boot clock source)

5 us (max.) starting time (time from cancelation of SLEEP state to vector table read by the

CPU)

32.768 kHz(typ.) crystal oscillator

OSC1 oscillator circuit

Oscillation stop detection circuit included

EXOSC clock input

16.3 MHz (max.) square or sine wave input

Configurable system clock division ratio

Configurable system clock used at wake up from SLEEP state

Other

Operating clock frequency for the CPU and all peripheral circuits is selectable.

I/O port (PPORT)

Number of general-purpose I/O ports

19 bits (max.) (Pins are shared with the peripheral I/O.)

Number of input interrupt ports

8 bits

Timers

Watchdog timer (WDT)

Generates NMI or watchdog timer reset.

128 – 1 Hz counter, second/minute/hour/day/day of the week/month/year counters

Theoretical regulation function for 1-second correction

Real-time clock (RTCA)

Alarm and stopwatch functions

5 channels

16-bit timer (T16)

2 channels can generate the SPIA master clock.

Supply voltage detection circuit (SVD)

Detection level

20 levels (1.8 to 3.7 V)

Other

Intermittent operation mode

Generates an interrupt or hardware reset according to the detection level evaluation.

Serial interfaces

1 channel

UART (UART)

Baud-rate generator included, IrDA1.0 supported

2 channels

Synchronous Serial Interface (SPIA)

The 16-bit timer (T16) can be used for the baud-rate generator in master mode.

1 channel

I

Baud-rate generator included

LCD driver (LCD8A)

LCD output

32 SEG x 1 to 4 COM (max.), 28 SEG x 5 to 8 COM (max.)

LCD contrast

16 levels (2.55 to 3.44 V)