© 2001 Fairchild Semiconductor Corporation

DS005368

www.fairchildsemi.com

September 1983

Revised September 2001

MM74HC589

8-Bit Shift Registers

with Input Latches and 3-STATE Serial Output

General Description

The

MM74HC589

high

speed

shift

register

utilizes

advanced silicon-gate CMOS technology to achieve the

high noise immunity and low power consumption of stan-

dard CMOS integrated circuits, as well as the ability to

drive 15 LS-TTL loads.

The MM74HC589 comes in a 16-pin package and consists

of an 8-bit storage latch feeding a parallel-in, serial-out 8-

bit shift register. Data can also be entered serially the shift

register through the SER pin. Both the storage register and

shift register have positive-edge triggered clocks, RCK and

SCK, respectively. SLOAD pin controls parallel LOAD or

serial shift operations for the shift register. The shift register

has a 3-STATE output to enable the wire-ORing of multiple

devices on a serial bus.

The 74HC logic family is speed, function, and pin-out com-

patible with the standard 74LS logic family. All inputs are

protected from damage due to static discharge by internal

Features

s 8-bit parallel storage register inputs

s Wide operating voltage range: 2V–6V

s Shift register has direct overriding load

s Guaranteed shift frequency. . . DC to 30 MHz

s Low quiescent current: 80

µA maximum (74HC Series)

s 3-STATE output for ‘Wire-OR'

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Top View

Truth Table

Order Number

Package Number

Package Description

MM74HC589M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

MM74HC589SJ

M16D

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC589N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

RCK

SCK SLOAD OE

Function

XX

X

H

XX

X

L

↑

X

X

X

Data loaded into input latches

↑

X

L

X

Data loaded into shift register

from pins

H or L

X

L

X

Data loaded from latches to

shift register

X

↑

H

X

Shift register is shifted. Data

on SER pin is shifted in.

↑↑

H

X

Data is shifted in shift register,

and data is loaded into latches