September 1983

Revised February 1999

© 1999 Fairchild Semiconductor Corporation

DS005006.prf

www.fairchildsemi.com

MM74HC259

8-Bit Addressable Latch/3-to-8 Line Decoder

General Description

The MM74HC259 device utilizes advanced silicon-gate

CMOS technology to implement an 8-bit addressable latch,

designed for general purpose storage applications in digital

systems.

The MM74HC259 has a single data input (D), 8 latch out-

puts (Q1–Q8), 3 address inputs (A, B, and C), a common

enable input (G), and a common CLEAR input. To operate

this device as an addressable latch, data is held on the D

input, and the address of the latch into which the data is to

be entered is held on the A, B, and C inputs. When

ENABLE is taken LOW the data flows through to the

addressed output. The data is stored when ENABLE transi-

tions from LOW-to-HIGH. All unaddressed latches will

remain unaffected. With enable in the HIGH state the

device is deselected, and all latches remain in their previ-

ous state, unaffected by changes on the data or address

inputs. To eliminate the possibility of entering erroneous

data into the latches, the enable should be held HIGH

(inactive) while the address lines are changing.

If enable is held HIGH and CLEAR is taken LOW all eight

latches are cleared to a LOW state. If enable is LOW all

latches except the addressed latch will be cleared. The

addressed latch will instead follow the D input, effectively

implementing a 3-to-8 line decoder.

All inputs are protected from damage due to static dis-

Features

s Typical propagation delay: 18 ns

s Wide supply range: 2–6V

s Low input current: 1

µA maximum

s Low quiescent current: 80

µA maximum (74HC Series)

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Latch Selection Table

H

= HIGH level, L = LOW level

D

= the level at the data input

before the indicated steady-state input

conditions were established.

Order Number

Package Number Package Description

MM74HC259M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

MM74HC259SJ

M16D

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC259MTC

MTC16

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC259N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Select Inputs

Latch

C

B

A

Addressed

LLL

0

LL

H

1

LH

L

2

LH

H

3

HL

L

4

HL

H

5

HH

L

6

HHH

7