September 1983

Revised February 1999

© 1999 Fairchild Semiconductor Corporation

DS005319.prf

www.fairchildsemi.com

MM74HC175

Quad D-Type Flip-Flop With Clear

General Description

The MM74HC175 high speed D-type flip-flop with comple-

mentary outputs utilizes advanced silicon-gate CMOS

technology to achieve the high noise immunity and low

power consumption of standard CMOS integrated circuits,

along with the ability to drive 10 LS-TTL loads.

Information at the D inputs of the MM74HC175 is trans-

ferred to the Q and Q outputs on the positive going edge of

the clock pulse. Both true and complement outputs from

each flip flop are externally available. All four flip-flops are

controlled by a common clock and a common CLEAR.

Clearing is accomplished by a negative pulse at the

CLEAR input. All four Q outputs are cleared to a logical “0”

and all four Q outputs to a logical “1.”

The 74HC logic family is functionally as well as pin-out

compatible with the standard 74LS logic family. All inputs

are protected from damage due to static discharge by inter-

Features

s Typical propagation delay: 15 ns

s Wide operating supply voltage range: 2–6V

s Low input current: 1

µA maximum

s Low quiescent supply current: 80

µA maximum (74HC)

s High output drive current: 4 mA minimum (74HC)

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

Truth Table

(Each Flip-Flop)

H

= HIGH Level (steady state)

L

= LOW Level (steady state)

X

= Irrelevant

↑ = Transition from LOW-to-HIGH level

established

Order Number

Package Number

Package Description

MM74HC175M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

MM74HC175SJ

M16D

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC175MTC

MTC16

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC175N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Inputs

Outputs

Clear

Clock

D

Q

Q

LX

X

L

H

H

↑

HH

L

H

↑

LL

H

HL

X