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MGA-683P8-TR1G Datasheet(PDF) 1 Page - AVAGO TECHNOLOGIES LIMITED

Part # MGA-683P8-TR1G
Description  Low Noise And High Linearity Active Bias Low Noise Amplifi er
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Manufacturer  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Direct Link  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

MGA-683P8-TR1G Datasheet(HTML) 1 Page - AVAGO TECHNOLOGIES LIMITED

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MGA-683P8
Low Noise And High Linearity Active Bias
Low Noise Amplifier
Data Sheet
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 90 V (Class A)
ESD Human Body Model = 500 V (Class 1B)
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Description
Avago Technologies’ MGA-683P8 is an economical, easy-
to-use GaAs MMIC Low Noise Amplifier (LNA). The LNA
has low noise and high linearity achieved through the
use of Avago Technologies’ proprietary 0.25
m GaAs
Enhancement-mode pHEMT process. It is housed in a
miniature 2.0 x 2.0 x 0.75 mm3 8-pin Quad-Flat-Non-Lead
(QFN) package. It is designed for optimum use from 450
MHz up to 2 GHz. The compact footprint and low profile
coupled with low noise, high gain and high linearity make
the MGA-683P8 an ideal choice as a low noise amplifier for
cellular infrastructure for GSM and CDMA. For optimum
performance at higher frequency from 1.5 GHz to 4 GHz,
the MGA-684P8 is recommended. Both MGA-683P8 and
MGA-684P8 share the same package and pinout.
Pin Configuration and Package Marking
2.0 x 2.0 x 0.75 mm3 8-lead QFN
Features
 Low noise Figure
 High linearity performance
 GaAs E-pHEMT Technology[1]
 Low cost small package size: 2.0 x 2.0 x 0.75 mm3
 Excellent uniformity in product specifications
 Tape-and-Reel packaging option available
Specifications
900 MHz; 5 V, 40 mA
 17.8 dB Gain
 0.56 dB Noise Figure
 More than 20 dB Input Return Loss
 32.8 dBm Output IP3
 21.5 dBm Output Power at 1dB gain compression
Applications
 Low noise amplifier for cellular infrastructure for GSM
and CDMA.
 Other low noise application.
 Repeater, Metrocell/Picocell application.
Simplified Schematic
Pin 1 – Vbias
Pin 5 – Not Used
Pin 2 – RFinput
Pin 6 – Not Used
Pin 3 – Not Used
Pin 7 – RFoutput/Vdd
Pin 4 – Not Used
Pin 8 – Not Used
Centre tab - Ground
Top View
Bottom View
[2]
[1]
[3]
[4]
[7]
[8]
[6]
[5]
83X
[2]
[1]
[3]
[4]
[7]
[8]
[6]
[5]
Note:
 The schematic is shown with the assumption that similar PCB is used
for both MGA-683P8 and MGA-684P8.
 Detail of the components needed for this product is shown inTable 1.
 Enhancement mode technology employs positive gate voltage,
thereby eliminating the need of negative gate voltage associated
with conventional depletion mode devices.
 Good RF practice requires all unused pins to be earthed.
Rbias
C6
C3
C2
R2
L2
R1
L1
C1
C4
L3
RFin
RFout
Vdd
[1]
[2]
[3]
[4]
[8]
[7]
[6]
[5]
C5
Note:
Package marking provides orientation and identification
“83” = Device Code
“X” = Month Code


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