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ML4827IP-2 Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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ML4827IP-2 Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 16 page ML4827 PRODUCT SPECIFICATION 5 REV. 1.0.1 6/27/01 Notes: 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. Includes all bias currents to other circuits connected to the VFB pin. 3. Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x IAC x (VEAO - 1.5V) -1. PFC Minimum Duty Cycle VIEAO > 4.0V 0 % Maximum Duty Cycle VIEAO < 1.2V 90 95 % Output Low Voltage IOUT = –20mA 0.4 0.8 V IOUT = –100mA 0.8 2.0 V IOUT = 10mA, VCC = 8V 0.7 1.5 V Output High Voltage IOUT = 20mA 10 10.5 V IOUT = 100mA 9.5 10 V Rise/Fall Time CL = 1000pF 50 ns PWM Duty Cycle Range ML4827-1 0-44 0-47 0-50 % ML4827-2 0-64 0-70 0-74 % Output Low Voltage IOUT = -20mA 0.4 0.8 V IOUT = -100mA 0.8 2.0 V IOUT = 10mA, VCC = 8V 0.7 1.5 V Output High Voltage IOUT = 20mA 10 10.5 V IOUT = 100mA 9.5 10 V Rise/Fall Time CL = 1000pF 50 ns Supply Shunt Regulator Voltage (VCCZ) 12.8 13.5 14.2 V VCCZ Load Regulation 25mA < ICC < 55mA ±100 ±300 mV VCCZ Total Variation Load, Temp 12.4 14.6 V Start-up Current VCC = 11.8V, CL = 0 0.7 1.0 mA Operating Current VCC < VCCZ - 0.5V, CL = 0 16 19 mA Undervoltage Lockout Threshold 12 13 14 V Undervoltage Lockout Hysteresis 2.7 3.0 3.3 V Symbol Parameter Conditions Min. Typ. Max. Units Electrical Characteristics (Continued) |
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