10-Bit, 7.5Msps, Full-Duplex

Analog Front-End

6

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ELECTRICAL CHARACTERISTICS (continued)

amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

AD1 = 0 (default)

2.048

Full-Scale Reference

AD1 = 1

V

Analog Input Range

0 to

V

Analog Input Impedance

Measured at DC

500

k

Ω

Input-Leakage Current

Measured at unselected input from 0 to

±0.1

µA

Gain Error

GE

Includes reference error, AD1 = 0

-5

+5

%FS

Zero-Code Error

ZE

±2

mV

Differential Nonlinearity

DNL

±0.6

LSB

Integral Nonlinearity

INL

±0.6

LSB

Supply Current

210

µA

AUXILIARY DACs (DAC1, DAC2, DAC3)

Resolution

N

12

Bits

Integral Nonlinearity

INL

From code 100 to code 4000

±1.25

LSB

Differential Nonlinearity

DNL

Guaranteed monotonic over code 100 to

code 4000 (Note 2)

-1.0

±0.65

+1.2

LSB

Output-Voltage Low

Ω

0.2

V

Output-Voltage High

Ω

2.57

V

DC Output Impedance

DC output at midscale

4

Ω

Settling Time

From code 1024 to code 3072, within ±10

LSB

1µs

Glitch Impulse

From code 0 to code 4095

24

Rx ADC–Tx DAC TIMING CHARACTERISTICS

CLK Rise to Channel-I Output Data

Valid

Figure 3 (Note 2)

5.5

8.2

11.5

ns

CLK Fall to Channel-Q Output

Data Valid

Figure 3 (Note 2)

6.5

9.3

13.0

ns

I-DAC DATA to CLK Fall Setup

Time

Figure 5 (Note 2)

10

ns

Q-DAC DATA to CLK Rise Setup

Time

Figure 5 (Note 2)

10

ns

CLK Fall to I-DAC Data Hold Time

Figure 5 (Note 2)

0

ns

CLK Rise to Q-DAC Data Hold

Time

Figure 5 (Note 2)

0

ns

CLK Duty Cycle

50

%

CLK Duty-Cycle Variation

±15

%

Digital Output Rise/Fall Time

20% to 80%

2.4

ns