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ML4804 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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ML4804 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 14 page March 2001 PRELIMINARY ML4804 Power Factor Correction and PWM Controller Combo GENERAL DESCRIPTION The ML4804 is a controller for power factor corrected, switched mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-3-2 specification. Intended as a BiCMOS enhancement of the industry-standard ML4824, the ML4804 includes circuits for the implementation of leading edge, average current, “boost” type power factor correction and a trailing edge, pulse width modulator (PWM). It also includes a TriFault Detect™ function to help ensure that no unsafe conditions will result from single component failure in the PFC. 1A gate-drive outputs minimize the need for external driver circuits. Low power requirements improve efficiency and reduce component costs. An over voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. The PWM section can be operated in current or voltage mode, at up to 250kHz, and includes an accurate 50% duty cycle limit to prevent transformer saturation. FEATURES I Internally synchronized leading-edge modulated PFC and trailing-edge modulated PWM in one IC I TriFault DetectTM for UL1950 compliance and enhanced safety I VCCOVP provides additonal PFC fault protection I Slew rate enhanced transconductance error amplifier for ultra-fast PFC response I Low power: 200 µA startup current, 5.5mA operating current I Low total harmonic distortion, high PF I Reduces ripple current in the storage capacitor between the PFC and PWM sections I Average current, continuous boost leading edge PFC I PWM configurable for current-mode or voltage mode operation I Overvoltage and brown-out protection, UVLO, and soft start BLOCK DIAGRAM 15 VEAO IEAO VFB IAC VRMS ISENSE RAMP 1 OSCILLATOR OVP VCCOVP TRI-FAULT PFC ILIMIT UVLO VREF PULSE WIDTH MODULATOR POWER FACTOR CORRECTOR 2.5V + - - + 16 2 4 3 7.5V REFERENCE 14 VCC 13 VCC VEA 7 IEA 1 + - PFC OUT 12 S R Q Q S R Q Q 2.75V VCC -1V RAMP 2 8 PWM OUT 11 S R Q Q VDC 6 SS 5 DC ILIMIT 9 VCC DUTY CYCLE LIMIT - + 1.0V - + 2.45V VFB - + VREF VIN OK GAIN MODULATOR VCC 1.6k Ω 1.6k Ω 1.25V 25µA - + DC ILIMIT + – 16.4V 0.5V + – + - - + 17V REV. 1.0.2 3/9/2001 |
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