ICM7115

Rev. 2.5

ICmic reserves the right to change the specifications without prior notice

2

PIN DESCRIPTION

Pin No

Symbol

Description

1

AGND

Analog Ground

1.4V regulated voltage output. Used by internal amplifiers. External capacitor

about 100uF should be connected to this pin.

2

VDD

Regulated Supply Voltage

When HS_DPB pin is HIGH, the VDD pin is regulated to 3.5V, and the input

power is extracted from VDDI pin. When HS_DPB is LOW, VDD should be

externally powered and it must not fall below 1.0V to retain the redial

memory. Most internal circuits are powered by VDD pin.

3

VDDI

Supply Input Voltage

Power for the chip is extracted from this VDDI pin. See also VDD pin

description. At steady state, VDDI is regulated to 4.3V by use of external PNP

transistor whose base terminal is connected to the TXO pin. See typical

application circuit. The external PNP transistor also functions to drain the

excess line current.

4

GND

Ground

5

TXO

Transmit Output

Transmit output is to be connected to external PNP transistor (typically

medium power PNP) for the modulation of line voltage and for shorting the

line during make period of pulse dialing. See the typical application circuit. The

external PNP transistor also functions to drain the excess line current.

6

VL

Line Voltage

If line-loss compensation (LLC) scheme is not used, then this pin can be

shorted to GND. If LLC scheme is used, then this pin is used to sense the line

current. The sense resistor (R11 in typical application circuit) must be 30 ohm

for the LLC scheme to work properly. The receive and transmit gains are

adjusted according to the sensed current and the chosen LLC scheme. See

also description on “Line Loss Compensation” section. Since VL pin will

typically experience high transient voltage, it is advisable to properly add

external protection circuit to suppress the high transient voltage which can

damage the pin.

7

LLC

Line Loss Compensation

Line loss compensation scheme options:

LLC=GND

- No LLC scheme.

LLC=AGND

- “Low” LLC scheme.

LLC=VDD

- “High” LLC scheme.

The receive and transmit gains are adjusted according to the sensed current

and the chosen LLC scheme. See description on “Line Loss Compensation”

section.

8

FOPT0

Flash Option

Flash duration options:

GND (logic 0) – 300ms flash duration.

VDD (logic 1) – 600ms flash duration.

9

MFL0

DTMF Option

Transmitted DTMF level options:

GND (logic 0): typical -8/-10dB.

VDD (logic 1): typical -6/-8dB.

10

HS_DPB

Hook Switch Input and Dial Pulse Output

When off-hook, this pin needs to be pulled HIGH (by the hook switch) to

activate the speech and dialer circuits. When on-hook this pin needs to be

pulled LOW to activate ringer circuit and deactivate speech and dialer circuits.

During pulse dialing (while off-hook, and pulse dialing mode is chosen), this

pin is pulled LOW during line-break periods.