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EVAL-ADV7623EB1Z Datasheet(PDF) 6 Page - Analog Devices |
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EVAL-ADV7623EB1Z Datasheet(HTML) 6 Page - Analog Devices |
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6 / 16 page  ADV7623 Data Sheet Rev. D | Page 6 of 16 Timing Diagrams xDA xCL t5 t3 t4 t8 t6 t7 t2 t1 t3 NOTES 1. x REFERS TO S, DDCA_S, DDCB_S, DDCC_S, DDCD_S. Figure 2. I2C Timing SCLK LRCLK I2S[3:0] LEFT-JUSTIFIED MODE I2S[3:0] RIGHT-JUSTIFIED MODE I2S[3:0] I2S MODE MSB MSB – 1 t13 t14 t15 t17 t18 t16 MSB MSB – 1 LSB MSB t17 t18 t17 t18 Figure 3. I2S Output Timing VALID DATA VALID DATA I2S[3:0], LRCLK SCLK RISING EDGE R0x0B[6] = 0 SCLK FALLING EDGE R0x0B[6] = 1 I2S[3:0] LRCLK t19 t20 t19 t20 Figure 4. I2S Input Timing |
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