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EVAL-AD7841EBZ Datasheet(PDF) 3 Page - Analog Devices |
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EVAL-AD7841EBZ Datasheet(HTML) 3 Page - Analog Devices |
3 / 13 page –3– AD7841 (These characteristics are included for Design Guidance and are not subject to production testing.) AC PERFORMANCE CHARACTERISTICS A & B Parameter Versions Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 31 µs typ Full-Scale Change to ±1/2 LSB. DAC Latch Contents Alternately Loaded with All 0s and All 1s Slew Rate 0.7 V/ µs typ Digital-to-Analog Glitch Impulse 230 nV-s typ Measured with VREF(+) = +5 V, VREF(–) = –5 V. DAC Latch Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent on Load Conditions Channel-to-Channel Isolation 99 dB typ See Terminology DAC-to-DAC Crosstalk 40 nV-s typ See Terminology Digital Crosstalk 0.2 nV-s typ Feedthrough to DAC Output Under Test Due to Change in Digital Input Code to Another Converter Digital Feedthrough 0.1 nV-s typ Effect of Input Bus Activity on DAC Output Under Test Output Noise Spectral Density @ 1 kHz 200 nV/ √Hz typ All 1s Loaded to DAC. VREF(+) = VREF(–) = 0 V Specifications subject to change without notice. TIMING SPECIFICATIONS1, 2 Parameter Limit at TMIN, TMAX Unit Description t1 15 ns min Address to WR Setup Time t2 0 ns min Address to WR Hold Time t3 50 ns min CS Pulsewidth Low t4 50 ns min WR Pulsewidth Low t5 0 ns min CS to WR Setup Time t6 0 ns min WR to CS Hold Time t7 20 ns min Data Setup Time t8 0 ns min Data Hold Time t9 31 µs typ Settling Time t10 300 ns max CLR Pulse Activation Time t11 50 ns min LDAC Pulsewidth Low NOTES 1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2Rise and fall times should be no longer than 50 ns. Specifications subject to change without notice. t1 t2 t5 t6 t3 t4 t7 t8 t9 t10 t11 LDAC CLR WR CS A0, A1, A2 DATA VOUT VOUT Figure 1. Timing Diagram (VCC = 5 V 5%; VDD = 15 V 10%; VSS = –15 V 10%; GND = DUTGND = 0 V) REV. B |
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