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CAT93C66 Datasheet(PDF) 6 Page - ON Semiconductor |
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CAT93C66 Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 16 page CAT93C66, CAT93W66 http://onsemi.com 6 Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C66, CAT93W66 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). For the CAT93C66, CAT93W66 after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. The READ instruction timing is illustrated in Figure 3. Erase/Write Enable and Disable The device powers up in the write disable state. Any writing after power−up or after an EWDS (erase/write disable) instruction must first be preceded by the EWEN (erase/write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C66, CAT93W66 write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. The EWEN and EWDS instructions timing is shown in Figure 4. Figure 2. Synchronous Data Timing SK DI CS DO VALID VALID DATA VALID tCSS tDIS tSKHI tSKLOW tDIS tDIH tCSH tCSMIN tPD0, tPD1 Figure 3. READ Instruction Timing SK CS DI DO HIGH−Z 11 0 Dummy 0 Don’t Care AN AN−1 tPD0 A0 Address + n D15 . . . or D7 . . . Address + 2 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 D15 . . . D0 or D7 . . . D0 |
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