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NSBC124EDXV6T1 Datasheet(PDF) 1 Page - ON Semiconductor |
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NSBC124EDXV6T1 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 9 page © Semiconductor Components Industries, LLC, 2012 September, 2012 − Rev. 7 1 Publication Order Number: NSBC114EDXV6/D NSBC114EDXV6T1, NSBC114EDXV6T5 Dual Bias Resistor Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminates these individual components by integrating them into a single device. In the NSBC114EDXV6T1 series, two BRT devices are housed in the SOT−563 package which is ideal for low power surface mount applications where board space is at a premium. Features • Simplifies Circuit Design • Reduces Board Space • Reduces Component Count • Lead−Free Solder Plating • These are Pb−Free Devices • NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1 and Q2) Rating Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current IC 100 mAdc THERMAL CHARACTERISTICS Characteristic (One Junction Heated) Symbol Max Unit Total Device Dissipation; TA = 25°C Derate above 25°C PD 357 (Note 1) 2.9 (Note 1) mW mW/°C Thermal Resistance, Junction-to-Ambient RqJA 350 (Note 1) °C/W Characteristic (Both Junctions Heated) Symbol Max Unit Total Device Dissipation; TA = 25°C Derate above 25°C PD 500 (Note 1) 4.0 (Note 1) mW mW/°C Thermal Resistance, Junction-to-Ambient RqJA 250 (Note 1) °C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C 1. FR−4 @ Minimum Pad NSBC114EDXV6T1 DEVICE MARKING INFORMATION See specific marking information in the device marking table on page 2 of this data sheet. Q1 R1 R2 R2 R1 Q2 (1) (2) (3) (4) (5) (6) SOT−563 CASE 463A 1 xx = Device Code (Refer to Page 2) M = Date Code G = Pb−Free Package MARKING DIAGRAM http://onsemi.com Device Package Shipping† ORDERING INFORMATION NSBC1xxxDXV6T1 SOT−563 4000/Tape & Reel NSBC1xxxDXV6T5 SOT−563 8000/Tape & Reel xx M G 1 NSBC1xxxDXV6T1G SOT−563 4000/Tape & Reel NSBC1xxxDXV6T5G SOT−563 8000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NSVBC1xxxDXV6T1G SOT−563 4000/Tape & Reel |
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